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Array signal processing

Publisher Summary The term “parallel processing” designates the simultaneous execution of multiple processors to solve a single computational problem cooperatively. Parallel processing has the potential for making difficult computational problems tractable by significantly increasing computer performance. Two basic kinds of computational problems are encouraging research in parallel processing through their need for orders-of-magnitude improvements in computer processing speed. First, problems characterized by inordinate size and complexity that often require hours or days of conventional processing. Secondly, real-time problems that requires the computations to be performed within a strictly defined time period and are typically driven by external events. These computational problems call for vast performance increases that conventional, single-processor computers are unlikely to provide. The primary barriers for achieving this kind of performance improvement through parallel processing; however, are conceptual ones, such as finding efficient ways to partition a problem among many processors and to orchestrate multiple processors executing in a cooperative fashion. Parallel processing must be supported by architectures that are carefully structured for coordinating the work of many processors and for supporting efficient interprocessor communications. The chapter discusses the major classes of parallel architecture—synchronous architectures, multiple instruction streams, multiple data streams (MIMD) Architectures, and MIMD execution paradigm architectures—describing their structure and how they function.

Parallel Computer Architectures

Key references in distributed computer systems 1959–1989

A parallel square-root algorithm and its systolic array implementation are proposed for performing modified extended Kalman filtering (MEKF). The proposed parallel square-root algorithm is designed based on the singular value decomposition (SVD) and the Faddeev algorithm, and a very large scale integration (VLSI) systolic array architecture is developed for its implementation. Compared to other square root Kalman filtering algorithms, the proposed method is more numerically stable. The VLSI architecture described has good parallel and pipelining characteristics in applying to the MEKF and achieves higher efficiency. For n-dimensional state vector estimations, the proposed architecture consists of O(2n/sup 2/) processing elements and uses O((s+17)n) time-steps for a complete iteration at each instant, in contrast to the complexity of O((s+6)n/sup 3/) time-steps for a sequential implementation, where s approximately=log n. >

A parallel square-root algorithm for modified extended Kalman filter

We propose in this paper a massively parallel machine dedicated to image synthesis by discrete ray tracing techniques. This machine is a four-stage pipeline, the last stage being a bidimensional cellular array with one cell per pixel. Two main phases describe its behaviour: · Loading into the cellular array of the objects of the scene to be displayed, after having been transformed into sets of planar polygons, and then into voxels. · Cellular ray tracing over the fully distributed scene.

The first phase allows us to see this machine as a massively parallel (not realistic) rendering unit: at the end of the loading phase: objects are fully identified pixel per pixel in the cellular array. Then, we have only to display the computed visual features (by means of Gouraud or Phong-like incremental methods during the loading phase).

The second phase increases the image quality by executing the ray tracing algorithm in a very special way, i.e., completely distributed all over the many cells of the array. In that phase, objects are seen as split into voxels into a virtual 3D memory space. The machine is an attempt to bring a dramatic answer to the problem of performance, taking into account not only the computational power required for image synthesis by using a massive parallelism, but also the realization costs by using very regular structures, which make it a VLSI-oriented architecture.

A cellular architecture for ray tracing

Systolic array computer architectures provide a means for fast computation of the linear algebra algorithms that form the building blocks of many signal-processing algorithms, facilitating their real-time computation. For applications to signal processing, the systolic array operates on matrices, an inherently parallel view of the data, using numerical linear algebra algorithms that have been suitably parallelized to efficiently utilize the available hardware. This article describes work currently underway at the Naval Ocean Systems Center, San Diego, California, to build a two-dimensional systolic array, SLAPP, demonstrating efficient and modular parallelization of key matric computations for real-time signal- and image-processing problems.

SLAPP: A Systolic Linear Algebra Parallel Processor

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SLAPP: A Systolic Linear Algebra Parallel Processor