This paper investigates advanced parallel processing techniques and innovative hardware/software architectures that can be applied to boost the performance of supercomputers. Critical issues on architectural choices, parallel languages, compiling techniques, resource management, concurrency control, programming environment, parallel algorithms, and performance enhancement methods are examined and the best answers are presented. We cover advanced processing techniques suitable for supercomputers, high-end mainframes, minisupers, and array processors. The coverage emphasizes vectorization, multitasking, multiprocessing, and distributed computing. In order to achieve these operation modes, parallel languages, smart compilers, synchronization mechanisms, load balancing methods, mapping parallel algorithms, operating system functions, application library, and multidiscipline interactions are investigated to ensure high performance. At the end, we assess the potentials of optical and neural technologies for developing future supercomputers.

Advanced parallel processing with supercomputer architectures

From the Publisher:
In order to achieve the computing power and speed necessary for their given applications, today's computers utilize numerous microprocessors working in conjunction with central processing units (CPU) on a single integrated circuit (IC) chip. This book presents expert, state-of-the-art discussion of advanced computer architecture, covering in detail such issues as caching, instruction-level parallelism, system bottlenecks, multithreading, multiprocessing, and distributed shared memory systems.

Surviving the Design of Microprocessor and Multimicroprocessor Systems: Lessons Learned

A successful technique forimproving system perfor- mancehasbeen tomigrate often used software functions into firmware. Anextension ofthis technique, called vertical migration, hasbeen developed thatdeals withmigrations offunctions between anytwo levels inamultilevel interpretive hierarchy. Inboth ofthese approaches theeffect ofmultiple migrations onsystem performance isnotfully understood andhasnotbeenformally analyzed. Inthis paper theeffects ofmultiple migrations onsystem performance areformally described. Threedistinct types ofmigration areidentified andformulas forthe execution timesavings ofeachtype arederived. IndexTerms-Firmware, interpretive model, performance im- provement, vertical migration. I.INTRODUCTION A SUCCESSFULtechnique forimproving system per- 16 formance hasbeentomigrate often usedsoftware functions into firmware. Anextension ofthis technique, called vertical migration (VM)(12), (15), hasbeendeveloped that deals withmigrations offunctions between anytwolevels in amultilevel interpretive hierarchy. Inbothofthese approaches theeffect ofmultiple migrations onsystem performance isnot fully understood andhasnotbeenformally analyzed. Inthis paper, using amultilevel interpreter model, theeffects of multiple migrations onsystem performance areformally de- scribed. Itisshownthat theinteraction ofmultiple migrations canactually produce greater performance improvement than thesumofthesavings ofeachmigration doneseparately. The paper also classifies three distinct types ofmigration which are named: vertical migration, newtarget instructions, andre- placement. Formulas fortheexecution timesavings ofeach type arederived. Theformulas showthat vertical migration haspotential forgreatest performance improvement andthat replacement, ifoneisnotcareful, canactually degrade per- formance. Allthese results areofusetosystem programmers whomight begiven thetaskofimplementing migrations. InSection IIageneral multilevel hierarchical performance model, called theVM model, isdescribed. Thismodel illus- trates theperformance improvement attainable byvertical migration. InSection IIIthemodel isthenused toillustrate several results concerning theinteraction ofmultiple vertical

The types and interactions of vertical migrations of functions in a multilevel interpretive system

An overview is provided of existing gallium arsenide microprocessors and related digital designs. The architectures described cover a wide range of applications and were chosen on the basis of their unique design and technology characteristics. The issues considered relate to the processor-design level with some register-transfer-level components covered for the sake of completeness. The discussion covers general-application microprocessors including: RCA 8-bit microprocessor; CDC 32-bit microprocessor; McDonnell Douglas 32-bit microprocessor; and RCA 32-bit microprocessor microprocessors of symbolic applications including: Carnegie Mellon's RISCF; and GAELIC from Magnavox, systolic array processors, and alternative approaches to processor design. >

GaAs microprocessors and digital systems: an overview of R&D efforts

(2m± 1) [HGS83b]. (d, k) [MR82]. (N,K) [KK86]. 1 [wu87b]. 1/2 [ZW87]. 2 [FLN89, Jes80a, KR82, RY82]. 2(log2N)− 1 [Lee85b]. 2/3 [ZW87]. 22n+ 1 [STR87]. 2m [PNH88]. 3 [WH88]. 4 [KW81, TPSS85]. 5.8n log2 n [CW80]. 8 [Kal83]. [lgN + 1] [CT84a]. 2 [DD81, Eti80, FM89]. 2.5 [DM84]. p [SLS82]. n [HSE84]. AB [Bla83, Slo85]. D [Kak85, Kak83, LB88, SW82, WV87, WR81]. d > t [LB88]. ` [Hoc83]. GF (2) [Fen89, WTS85, YRT84, Zho88]. GF (P ) [TKL86, HQR89]. GF [p] [Eng81]. K [GM87, NHAT89, Agg86, BL84, CI88, CE87, Dav89, Lee82, LC87b]. L/U [JK82]. λT [CGMP87]. M [Bla83, Mor80, Slo85, WH80a, Wus81, GH83b, HGS83b, PNH88]. m2 [MM83a]. N [CS87, Er84, Esf89, Mor80, Wus81, AP89, AG81b, Bha83a, GH83b, Kha82, LM87a]. n− 1/n [Nil84, Wen85, Can83]. O(2) [Jia86]. O(log n) [BP85]. O(n) [Sip82]. O(n+ k) [LD88]. O(N/ log N) [SR81a]. O(t + |E|) [Sul88]. P [Tha82, Tha84b, TKL86, YF88, Fro83, GNK86, KM83b, Wus82]. r [GH83a, HGS83a]. s [SSS89]. t [BV89, CA89, LB88, NGP86].

/pdf/a-bibliography-of-ieee-transactions-on-computers-1980-1989-4w2o1p889u.pdf

A Bibliography of IEEE Transactions on Computers (1980{1989)

This paper analyzes the potential performance of a high-level language (HLL) microprocessor architecture for special- purpose real-time applications. Our approach is based on mapping of HLL constructs into microcode, a concept called vertical migration. An analytical execution-time model of the reduced vertical-migration architecture is developed. It is applied to two different workload models: one corresponding to statement mixes, and the other showing some HLL kernel routines. Performance evaluation results are compared to different forms of the reduced vertical-migration architecture, and in various application domains. We underline in this paper the, basic relationships among microprocessor architecture, GaAs technology, and real-time applications.

A GaAs-Based Microprocessor Architecture for Real-Time Applications

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A GaAs-Based Microprocessor Architecture for Real-Time Applications