Loic Sanchez
University of Grenoble
52 Papers
409 Citations
Loic Sanchez is an academic researcher from University of Grenoble. The author has contributed to research in topics: Wafer & Direct bonding. The author has an hindex of 13, co-authored 47 publications. Previous affiliations of Loic Sanchez include French Alternative Energies and Atomic Energy Commission & Commissariat à l'énergie atomique et aux énergies alternatives.
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Papers
Advances, challenges and opportunities in 3D CMOS sequential integration
Perrine Batude,Maud Vinet,Bernard Previtali,Claude Tabone,Cuiqin Xu,J. Mazurier,Olivier Weber,Francois Andrieu,L. Tosti,L. Brevard,Benoit Sklenard,Perceval Coudrain,Shashikanth Bobba,H. Ben Jamaa,P.-E. Gaillardon,A. Pouydebasque,Olivier P. Thomas,C. Le Royer,J.M. Hartmann,Loic Sanchez,L. Baud,V. Carron,Laurent Clavelier,G. De Micheli,Simon Deleonibus,O. Faynot,Thierry Poiroux +26 more
- 01 Dec 2011
TL;DR: This paper addresses the major challenges of 3D sequential integration: in particular, the control of molecular bonding allows us to obtain pristine quality top active layer and can match the performance of top FET, processed at low temperature (600°C), with the bottom FET devices.
Advances in 3D CMOS sequential integration
Perrine Batude,Maud Vinet,A. Pouydebasque,C. Le Royer,Bernard Previtali,Claude Tabone,J.M. Hartmann,Loic Sanchez,L. Baud,V. Carron,Alain Toffoli,F. Allain,V. Mazzocchi,D. Lafond,Olivier P. Thomas,O. Cueto,N. Bouzaida,D. Fleury,Amara Amara,Simon Deleonibus,O. Faynot +20 more
- 01 Dec 2009
TL;DR: In this article, a 3D sequential CMOS integration of top Si active layers is presented, and the electrostatic coupling between stacked FETs is demonstrated thanks to an ultra thin inter layer dielectric thickness of 60nm.
170
3D monolithic integration: Technological challenges and electrical results
Maud Vinet,Perrine Batude,Claude Tabone,Bernard Previtali,C. LeRoyer,A. Pouydebasque,Laurent Clavelier,A. Valentian,Olivier P. Thomas,S. Michaud,Loic Sanchez,L. Baud,A. Roman,V. Carron,Fabrice Nemouchi,V. Mazzocchi,H. Grampeix,Amara Amara,Simon Deleonibus,O. Faynot +19 more
TL;DR: In this paper, the main technological challenges associated with monolithic 3D integration are reviewed and solutions to assess them are proposed, and the electrical results obtained within this integration scheme are summarized: mixed Ge over Si invertor is demonstrated and electrostatic coupling between top and bottom layer is used to shift the threshold voltage of the top layer.
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3D monolithic integration
Perrine Batude,Maud Vinet,A. Pouydebasque,C. Le Royer,Bernard Previtali,Claude Tabone,J.M. Hartmann,Loic Sanchez,L. Baud,V. Carron,Alain Toffoli,F. Allain,V. Mazzocchi,D. Lafond,Simon Deleonibus,O. Faynot +15 more
- 15 May 2011
TL;DR: A 3D monolithic process flow relying on molecular wafer bonding is proposed and results in all critical steps are given and functional top and bottom transistors as well as 3D structures such as invertors and SRAMs are demonstrated.
87
High performance 70 nm gate length germanium-on-insulator pMOSFET with high-k/metal gate
K. Romanjek,Louis Hutin,C. Le Royer,A. Pouydebasque,Marie-Anne Jaud,Claude Tabone,E. Augendre,Loic Sanchez,J.M. Hartmann,H. Grampeix,V. Mazzocchi,S. Soliveres,R. Truche,Laurent Clavelier,P. Scheiblin,X. Garros,G. Reimbold,Maud Vinet,Fabien Boulanger,Simon Deleonibus +19 more
TL;DR: In this paper, the authors demonstrate for the first time 70nm gate length gate length TiN/HfO 2 pMOSFETs on 200mm GeOI wafers, with excellent performance: I ON Â= 260μA/μm and I OFF Â = 500 Ã 1.0 Â V (without germanide).
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