With the development of the cloud-based Internet of Things (IoT), people and things can request services, access data, or control actuators located thousands of miles away. The entity authentication of the remotely accessed devices is an essential part of the security systems. In this vein, physical unclonable functions (PUFs) are a hot research topic, especially for generating random, stable, and tamper-resistant fingerprints. This article proposes a lightweight, robust static random access memory (SRAM)-PUF-based entity authentication scheme to guarantee that the accessed end devices are trustable. The proposed scheme uses challenge-response pairs (CRPs) represented by reordered memory addresses as challenges and the corresponding SRAM cells’ startup values as responses. The experimental results show that our scheme can efficiently authenticate resources-constrained IoT devices with a low computation overhead and small memory capacity. Furthermore, we analyze the SRAM-PUF by testing the PUF output under different environmental conditions, including temperature and magnetic field, in addition to exploring the effect of writing different values to the SRAM cells on the stability of their startup values.

/pdf/sram-puf-based-entities-authentication-scheme-for-resource-3cwxtisx38.pdf

SRAM-PUF-Based Entities Authentication Scheme for Resource-Constrained IoT Devices

FPGA-based Physical Unclonable Functions: A comprehensive overview of theory and architectures

Lightweight electronic devices are emerging as a promising electronic equipment. Physical unclonable function (PUF), a kind of authentication circuit in lightweight electronic chip, is very useful component in secure system design. The reliability and uniqueness of PUF is limited by the complexity of its circuit. Herein, a reconfigurable XOR gate PUF based on configurable delay line is demonstrated to obtain lightweight chip certification circuit. Owing to the same number of configurable logic blocks (CLBs) in the FPGA implementation, the PUF can generate more challenge response pair (CRP) well. The PUF exhibits a much better uniqueness and reliability than previous other types of PUF designs when this design is implemented in multiple Xilinx Virtex-6 FPGAs. Moreover, this PUF consumes less than 0.05% of hardware resources to generate a 1-bit response than other configurable PUFs implemented in FPGA.

A Lightweight Configurable XOR RO-PUF Design Based on Xilinx FPGA

A physical unclonable function (PUF) device using a nano-electromechanical (NEM) switch was demonstrated. The most important feature of the NEM-switch-based PUF is its use of stiction. Stiction is one of the chronic problems associated with micro- and nano-electromechanical system (MEMS/NEMS) devices; however, here, it was utilized to intentionally implement a PUF for hardware-based security. The stiction is caused by capillary and van der Waals forces, producing strong adhesion, which can be utilized to design a highly robust and stable PUF. The probability that stiction will occur on either of two gates in the NEM switch is the same, and consequently, the occurrence of the stiction is random and unique, which is critical to its PUF performance. This uniqueness was evaluated by measuring the interchip Hamming distance (interchip HD), which characterizes how different responses are made when the same challenge is applied. Uniformity was also evaluated by the proportion of "1" or "0" in the response bit-string. The reliability of the proposed PUF device was assessed by stress tests under harsh environments such as high temperature, high dose radiation, and microwaves.

Nano-electromechanical switch based on a physical unclonable function for highly robust and stable performance in harsh environments = 열악한 환경에서의 견고하고 안정적인 성능을 위한 나노전자기계 스위치 기반의 물리적 복제 방지 기능

Hardware security modules play a crucial role in protecting and preserving technologically integrated systems that are used in daily life. They employ cryptographic protocols to secure a system against adversaries. Generally, cryptographic algorithms and security keys are quintessential for maintaining the security of a system. Cryptography uses a secret key to encipher and decipher the data. These secret keys are stored in a non-volatile memory that attackers can easily access. The hardware security primitive, Physical Unclonable Function (PUF) is a promising alternative for enhancing the security of interconnected devices. A PUF produces an output in response to an input based on physical structure and intrinsic manufacturing variations of an integrated circuit (IC). The generated random response being unpredictable, act as a robust secret key in cryptographic protocols. The first silicon PUF is the Arbiter PUF, which can instantly produce significantly more secret keys based on the input with a lightweight design. Due to its advantage, it is best suited for device authentication in resource-constrained applications employing the Internet of Things (IoT). The PUF is also suitable for applications such as the Internet of Vehicles, the Internet of Medical Things, RFID tags, and smart cards. In this paper, the basic Arbiter PUF design is implemented in ZedBoard to analyze the PUF performance characteristics for 16, 32, and 64-bit responses. A review of Arbiter PUF design, different compositions of Arbiter PUF, their individual characteristics, and vulnerabilities against machine-learning attacks have been presented at their broader best in this paper. 

Arbiter PUF - A Review of Design, Composition, and Security Aspects

Physical unclonable function (PUF) is hardware-specific security primitive for providing cryptographic functionalities that are applicable for secure communication among the embedded devices. The physical structure of PUF is considered to be easy to manufacture but hard or impossible to replicate due to variations in its manufacturing process. However, a large community of analytics believes hardware-based PUF has paved the way for its realisation in providing dependable security. In this study, the authors have thoroughly explored the architecture, applications, requirements, and challenges of PUF that provide security solutions. For presenting the literature, they have designed a taxonomy where PUFs are divided under two main categories, including non-silicon and silicon-based PUF. Currently, there is no comprehensive survey that highlights the comparison and usability of memory-based and analogue/mixed-signal based PUF that are considered to be suitable as compared to counterparts. In a similar vein, they have presented the network-specific application scenarios in wireless sensor network, wireless body area network and Internet of Things and then identified the strong, weak and controlled PUF in a categorical manner. Moreover, they have presented a number of prospective limitations that are identified in PUF structures and then identified the open research challenges to meet the desired security levels.

https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/iet-cds.2019.0175

Physical unclonable function: architectures, applications and challenges for dependable security

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Physical unclonable function: architectures, applications and challenges for dependable security