Smoothed Particle Hydrodynamics (SPH) is essential for modeling complex large-deformation problems across various applications, requiring significant computational power. A major portion of SPH computation time is dedicated to the Nearest Neighboring Particle Search (NNPS) process. While advanced NNPS algorithms have been developed to enhance SPH efficiency, the potential efficiency gains from modern computation hardware remain underexplored. This study investigates the impact of GPU parallel architecture, low-precision computing on GPUs, and GPU memory management on NNPS efficiency. Our approach employs a GPU-accelerated mixed-precision SPH framework, utilizing low-precision float-point 16 (FP16) for NNPS while maintaining high precision for other components. To ensure FP16 accuracy in NNPS, we introduce a Relative Coordinated-based Link List (RCLL) algorithm, storing FP16 relative coordinates of particles within background cells. Our testing results show three significant speedup rounds for CPU-based NNPS algorithms. The first comes from parallel GPU computations, with up to a 1000x efficiency gain. The second is achieved through low-precision GPU computing, where the proposed FP16-based RCLL algorithm offers a 1.5x efficiency improvement over the FP64-based approach on GPUs. By optimizing GPU memory bandwidth utilization, the efficiency of the FP16 RCLL algorithm can be further boosted by 2.7x, as demonstrated in an example with 1 million particles. Our code is released at https://github.com/pnnl/lpNNPS4SPH. 

A GPU accelerated mixed-precision Smoothed Particle Hydrodynamics framework with cell-based relative coordinates

Today’s desktop rendering platforms typically use GPUs, which have become the most powerful computing chip to meet the growing visual needs, especially in ray tracing. However, ray tracing is challenging for mobile platforms because mobile GPUs need to accommodate insufficient computing power, hardware resources, and memory bandwidth. This paper presents a novel architecture for the mobile domain called Mobile Multiple stacks Ray Tracing (MMsRT). The most complicated calculations in ray tracing are completed through lightweight embedded design. MMsRT has three key features: First, we set multiple stacks to ensure multiple rays are parallel in the system. Second, it sets a stack cache to store the data in stacks when the storage space of multiple stacks is insufficient. Third, we adopt the data prefetching mechanism to set caches to improve the cache hit rate and performance. An accurate simulator test proves that our design can be applied to mobile devices. We calculate the performance of about 82.9 Million Rays Per Second (MRPS), the chip area is about 0.856[Formula: see text]mm 2 , and 96.85[Formula: see text]MRPS/mm 2 . 

MMsRT: A Hardware Architecture for Ray Tracing in the Mobile Domain

RTA: an Efficient SIMD Architecture for Ray Tracing

To meet the demands of low-precision operations in deep learning, this paper presents two architectures for low-precision computation units. Firstly, we propose a low-cost and multi-precision multiplication unit to satisfy various precision requirements. Secondly, to satisfy the requirements of high-performance floating-point operations, we investigate the implementation of floating-point fused dot-product units and devise a scalable architecture supporting low-precision mixed operations. Experimental results demonstrate that compared to conventional multiplication units with the same function, the proposed multi-precision multiplication unit reduces area by 26.6 %; The dot-product units realized by the proposed dot-product architecture reduce the area by over half compared to equivalent arithmetic units, and the proposed dot-product architecture can easily implement fused dot-product units with higher throughput. The amalgamation of these two studies will enhance the floating-point computing capabilities significantly for deep-learning applications.

Low-Precision Vectorized Arithmetic Unit Designs for Deep Learning

In recent years, real-time ray tracing has attracted considerable attention with the increasing demand for photo-realistic graphics and rapid advances in CPUs/GPUs. However, efficient hardware architecture is challenging due to branches and high computation intensity for ray tracing. In this paper, we present a novel ray tracing hardware architecture called RTA (Ray Tracing Accelerator) to improve hardware efficiency. RTA has two key features: 1) an area-efficient T&I pipeline adopts three optimization strategies; 2) the configuration of two Ray Traversal units has the highest ray tracing efficiency. Combined with these, we implement our system at RTL level with agile chip development. Experimental results demonstrate that RTA's performance achieves $2.83\times$ higher than other academic and commercial architectures in a similar area.

The reality of the ray tracing technology that leads to its rendering effect is becoming increasingly apparent in computer vision and industrial applications. However, designing efficient ray tracing hardware is challenging due to memory access issues, divergent branches, and daunting computation intensity. This article presents a novel architecture, a RT engine (Ray Tracing engine), that accelerates ray tracing. First, we set up multiple stacks to store information for each ray so that the RT engine can process many rays parallel in the system. The information in these stacks can effectively improve the performance of the system. Second, we choose the three-phase break method during the triangle intersection test, which can make the loop break earlier. Third, the reciprocal unit adopts the approximation method, which combines Parabolic Synthesis and Second-Degree interpolation. Combined with these strategies, we implement our system at RTL level with agile chip development. Simulation and experimental results show that our architecture achieves a performance per area which is 2.4 × greater than the best reported results for ray tracing on dedicated hardware.

/pdf/rt-engine-an-efficient-hardware-architecture-for-ray-tracing-24ne3pw2.pdf

RT Engine: An Efficient Hardware Architecture for Ray Tracing

Low-precision formats have been proposed and applied to deep learning algorithms to speed up training and inference. This paper proposes a novel multiple-precision multiplication unit(MU) for deep learning. The proposed MU supports four types of precision for floating-point(FP) numbers-FP8-E4M3, FP8-E5M2, FP16, FP32-and 8-bit fixed-point(FIX) numbers. The MU can execute four parallel FP8 and eight parallel FIX8 multiplications simultaneously in one cycle, or four parallel FP16 multiplications fully pipelined with a latency of one, or one FP32 multiplication with a latency of one cycle. The simultaneous execution of FIX8 and FP8 can meet the requirements of the specific deep learning algorithms. Thanks to the low-precision-combination(LPC) and vectorization design method, multiplication in any precision can get 100% utilization of the multiplier resources, and the MU can adopt a lower clock delay to achieve better performance in all data types. Compared with the existing multiple-precision units designed for deep learning, this MU can support more types of low-precision formats by lower area overhead; and exhibits higher throughput at FIX8 with at least 8× improvement.

Low-Cost Multiple-Precision Multiplication Unit Design For Deep Learning

A high-performance configurable load storage unit (LSU) design is completed under the open source RISC-V framework. By compressing the pipeline depth, the module function structure is optimized under the premise of the control unit overhead, and the instruction processing speed is improved. In the method of instruction processing, a partial out-of-order processing strategy is adopted to control the increase of module complexity, reduce instruction blocking, and increase the density of instructions flowing into the LSU and the write back speed; redirection technology is adopted, and 3 channels are added when writing back data, which improve the speed of data write back, reduce instruction blocking, and ensure the correctness of the data; in order to support the partial out-of-order processing of the load and store instructions and the data redirection function, a double buffer design is adopted, the issue port and write-back port have been expanded to improve the transmission speed and write-back speed of the command. At the same time, the unit adopts a configurable way to expand the function, and separates the additional functions separately. It has good configurability and provides a good design for the next step of function expansion. Experimental results show that, after optimized design, LSU has increased the speed of existing processors by 63.5%, and has huge potential performance in processing high-density and read-related instructions, while the unit overhead has been reduced, the overall performance has been significantly improved.

The Design of High-performance and Configurable Load Storage Unit

In this paper, a multiple-precision and mixed-precision floating-point fused multiply-accumulate (FMA) unit is proposed base on the practical requirements of high performance computing (HPC) and artificial intelligence (AI) applications. In addition to the double-precision and single-precision formats used in high performance computing, three types of low-precision formats, TensorFloat-32, BFloat16, and half-precision, dedicated to deep learning tasks are also supported by this FMA unit. The proposed FMA architecture can execute one double-precision operation, or two parallel single-precision operations, or four half-precision operations at each clock cycle. Moreover, the mixed-precision FMA operations are also supported by this proposed FMA, the products of two lower precision multiplications can be accumulated to a higher precision addend. One mixed-precision operation using single-precision multiplication and double-precision addition, or two parallel mixed-precision operations using low-precision (TensorFloat-32, BFloat16, or half-precision) multiplication and single-precision addition is performed every clock cycle. The presented FMA design uses both segmentation and reusing methods to trade off performance, such as throughput and latency, against area and power. The proposed FMA unit has only 17.0% larger area than a standard double-precision FMA implementation, but can support multiple-precision and mixed-precision operations. Compared to the state-of-the-art multiple-precision FMA design, the proposed FMA supports more types of precisions such as TensorFloat-32 and BFloat16 with less hardware overhead. 

Efficient Multiple-Precision and Mixed-Precision Floating-Point Fused Multiply-Accumulate Unit for HPC and AI Applications

Stride prediction is a nonignorable part of value prediction. Most hybrid predictors cannot eliminate this pattern. Existing stride predictors can handle the regular stride pattern, but it is hard to fit well with the interval stride pattern. To deal with it, we introduce the notion of Stride Equality Prediction (SEP), which predicts the stride feature of the current instruction is equal to that of the last committed same instruction. SEP can deal well with interval-style stride patterns, which always perform a constant stride during an interval, although there may be different endpoints and strides in different intervals. SEP predicts the value of stride equality instructions from the last committed occurrence of the same instruction and the number of the same instruction in the instruction window. Evaluation results show that SEP is effective in stride value prediction. It outperforms the Enhanced Stride predictor for 5.3% and state-of-art computational predictor Context-based Computational Value TAGE (CBC-VTAGE) for 1.5% on average. Moreover, by applying the SEP update condition, CBC-VTAGE can obtain performance gain without extra cost.

Stride Equality Prediction for Value Speculation

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