In traditional von Neumann computing architectures, the essential transfer of data between the processor and memory hierarchies limits the computational efficiency of next-generation system-on-a-chip. The emerging in-memory computing (IMC) approach addresses this issue and facilitates the movement of significant data and rapid computations. Among the different memory types, intrinsic energy efficiency is demonstrated by in-magnetic random access memory (MRAM) computing with a low-power spintronic magnetic tunnel junction device and hybrid integration at an advanced complementary metal-oxide semiconductor node. This study reviews state-of-the-art techniques for managing IMC with an emphasis on spin-transfer torque-MRAM computing via design schemes at the bit-cell, circuit, and system levels. In addition, this study presents effective design techniques and potential challenges and demonstrates the existing limitations of in-MRAM computing and potential methods for overcoming these issues. This study also considers the design technology co-optimization from the IMC perspective.

A survey of in-spin transfer torque MRAM computing

Low-power keywords recognition has been a focus of acoustic signal processing for several decades. This work investigates the domain-specific speech recognition microprocessor based on optimized one-dimensional convolutional recurrent neural network (1D-CRNN). Compared to previous DNN based frameworks, the proposed 1D-CRNN can process both the feature extraction and keywords classification, and achieve high recognition accuracy with reduced computation operations under wide range background noise SNRs. An energy-efficient 1D-CRNN accelerator is implemented to dynamically reconfigure and process the different layers. This accelerator has the characteristics of “More is Less” in three aspects: 1) the hybrid network with more complex layers is much more compact and requires less computation; 2) although the weight width quantized to 8 bits requires more memory size and multiplication energy cost, the required network neurons can be reduced and hardware utilization can be improved; 3) an energy-aware self-compensation tensor multiplication unit with dual power supply based on approximation design method can be utilized for 1D-CRNN computing. Compared to the state-of-the-art architectures, the novel more-is-less architecture can achieve a much lower power consumption of $1.4~\mu \text{W}\sim 2.1~\mu \text{W}$ (over 80% reduced) under an industry 22nm technology, while maintaining higher system adaptability (support SNRs: −5dB~Clean) for 1~5 real-time keywords recognition.

More is Less: Domain-Specific Speech Recognition Microprocessor Using One-Dimensional Convolutional Recurrent Neural Network

Keyword spotting (KWS) is a crucial function enabling the interaction with the many ubiquitous smart devices in our surroundings, either activating them through wake-word or directly as a human-computer interface. For many applications, KWS is the entry point for our interactions with the device and, thus, an always-on workload. Many smart devices are mobile and their battery lifetime is heavily impacted by continuously running services. KWS and similar always-on services are thus the focus when optimizing the overall power consumption. This work addresses KWS energy-efficiency on low-cost microcontroller units (MCUs). We combine analog binary feature extraction with binary neural networks. By replacing the digital preprocessing with the proposed analog front-end, we show that the energy required for data acquisition and preprocessing can be reduced by <inline-formula> <tex-math notation="LaTeX">$29\times $ </tex-math></inline-formula>, cutting its share from a dominating 85% to a mere 16% of the overall energy consumption for our reference KWS application. Experimental evaluations on the Speech Commands Dataset show that the proposed system outperforms state-of-the-art accuracy and energy efficiency, respectively, by 1% and <inline-formula> <tex-math notation="LaTeX">$4.3\times $ </tex-math></inline-formula> on a 10-class dataset while providing a compelling accuracy-energy trade-off including a 2% accuracy drop for a <inline-formula> <tex-math notation="LaTeX">$71\times $ </tex-math></inline-formula> energy reduction.

https://zenodo.org/record/5960706/files/Keyword_Spotting_Cerutti.pdf

Sub-mW Keyword Spotting on an MCU: Analog Binary Feature Extraction and Binary Neural Networks

Face classification is important in many applications such as surveillance, border control, and security systems. However, wide variations in environments such as insufficient light, large distances or pose angles make the task challenging. Depth sensors are added with RGB cameras for improving classification accuracy but commercial RGB-D sensors are most targeted for indoors applications. In this paper, we present and design a Chaos LiDAR depth sesnor that provides high-precision depth images through intelligent correlation processing for both indoors and outdoors applications. Our Chaos LiDAR depth sensor detects range from 2 to 40 meters with precision around 8mm at 20-meter. With the Chaos LiDAR depth as input, we design a RGB-D based face classification embedded CNN (eCNN) model for wide range applications such as dim illumination, various distances and large poses. Our Chaos LiDAR increases around 14.27% classification accuracy compared to RealSense D435i for distance from 3 to 5 meter. The eCNN face classification subsystem is implemented in Xilinx ZCU 102 and achieves 11.11 ms inference time. The eCNN engine achieves a peak throughput at 614.4 GOPS. The overall system including Chaos LiDAR, correlation and eCNN FPGA achieves face classification inference rate of 10fps. 

Chaos LiDAR Based RGB-D Face Classification System With Embedded CNN Accelerator on FPGAs

CNN model computation on edge devices is tightly restricted to the limited resource and power budgets, which motivates the low-bit quantization technology to compress CNN models into 4-bit or lower format to reduce the model size and increase hardware efficiency. Most current low-bit quantization methods use uniform quantization that maps weight and activation values onto evenly-distributed levels, which usually results in accuracy loss due to distribution mismatch. Meanwhile, some non-uniform quantization methods propose specialized representation that can better match various distribution shapes but are usually difficult to be efficiently accelerated on hardware. In order to achieve low-bit quantization with high accuracy and hardware efficiency, this paper proposes Universal Power-of-Two (UPoT), a novel low-bit quantization method that represents values as the addition of multiple power-of-two values selected from a series of subsets. By updating the subset contents, UPoT can provide adaptive quantization levels for various distributions. For each CNN model layer, UPoT automatically searches for the optimized distribution that minimizes the quantization error. Moreover, we design an efficient accelerator system with specifically optimized power-of-two multipliers and requantization units. Evaluations show that the proposed architecture can provide high-performance CNN inference with reduced circuit area and energy, and outperforms several mainstream CNN accelerators with higher ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8\times $ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$65\times $ </tex-math></inline-formula> ) area efficiency and ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$19\times $ </tex-math></inline-formula> ) energy efficiency. Further experiments of 4/3/2-bit quantization on ResNet18/50, MobileNet_V2 and EfficientNet models show that our UPoT can achieve high model accuracy which greatly outperform other state-of-the-art low-bit quantization methods by 0.3%–6%. The results indicate that our approach provides a highly-efficient accelerator for low-bit CNN model quantization with low hardware overheads and good model accuracy. 

An Energy-and-Area-Efficient CNN Accelerator for Universal Powers-of-Two Quantization

This paper proposes a high power-performance-area efficient background noise aware keyword-spotting (KWS) processor based on an optimized binarized weight network (BWN). To reduce the power consumption while maintaining the system recognition accuracy for different background noise, the KWS processor with a SNR prediction module can be adaptively configured to use dual computing modes (standard computing mode and approximate computing mode) for both high recognition accuracy under high background noise and ultra-low power consumption under low background noise. The mel-scale frequency cepstral coefficients (MFCC) module is optimized with approximate computing technologies, which can reduce the power consumption by up to $3.1\times $ and $5.7\times $ for high/low background noise, respectively. Based on the evaluation of the architecture design space exploration, an ultra-low power BWN accelerator with low voltage, area and leakage power and using precision self-adaptive approximate computing units was proposed. Evaluated under 22nm process technology, this work can support up to 10 keywords real time recognition with power consumption of $15.1~\mu \text{W}$ for high background noise and $10.8~\mu \text{W}$ for low background noise. Compared to the state-of-the-art KWS architectures, our work can achieve ultra-low power consumption (about $1.7\times $ reduced), while maintaining high system capability and adaptability.

A 22nm, 10.8 μ W/15.1 μ W Dual Computing Modes High Power-Performance-Area Efficiency Domained Background Noise Aware Keyword- Spotting Processor

The invention discloses a deep neural network accelerator based on hybrid precision storage, and belongs to the technical field of calculation, reckoning and counting. The accelerator comprises an on-chip cache module, a control module, a bit-width-controllable multiply-add-batch calculation module, a nonlinear calculation module, a register array and a Huffman decoding module based on double lookup tables, effective bit and sign bit parameters of the weight are stored in the same memory, so that mixed-precision data storage and analysis are realized, and multiply-add operation of mixed-precision data and weight is realized. Through data storage analysis based on mixed precision and Huffman decoding based on a dual lookup table, compression and storage of data and weights under different precision are realized, data streams are reduced, and low-power-consumption data scheduling based on a deep neural network is realized.

Deep neural network accelerator based on hybrid precision storage

The invention provides a keyword recognition system based on a hybrid compression convolutional neural network, and belongs to the technical field of calculation, reckoning and counting. The system comprises an analog-to-digital conversion module, a feature extraction module and a hybrid compression convolutional neural network module. An input value of the convolutional neural network is subjected to high-order residual quantization, a weight value of the neural network is subjected to fine-grained progressive quantization and low-bit quantization of an activation value, and then a convolution kernel is subjected to pruning based on a front and back stage joint evaluation strategy, so that the parameter quantity and the model size of the network are reduced. The parameter quantity of theneural network is reduced through quantization, and the calculation amount of the network is reduced through pruning, so that the purpose of optimizing the network is achieved.

Keyword recognition system based on hybrid compression convolutional neural network

The invention discloses a selection method for calculating bit width of a multi-bit-width PE array and a calculation precision control circuit, and belongs to the technical field of calculation, reckoning and counting. According to the invention, the output probability value of the last Softmax layer of the neural network is analyzed to judge the output maximum probability so as to evaluate the network identification precision; whether the output maximum probability value meets the calculation precision requirement or not is judged through two set probability thresholds; if the maximum probability value is smaller than the minimum threshold value, the signal of the high bit width processing element array is adopted; if the maximum probability value is larger than the minimum threshold value and smaller than the maximum threshold value, the previous bit width processing element array is maintained, and if the maximum probability value is larger than the maximum threshold value, the signal of the low bit width processing element array is adopted, the maximum probability output by the network is maintained in a certain atmosphere, and the power consumption is reduced while the identification precision of the network is ensured.

Selection method for calculating bit width of multi-bit-width PE array and calculation precision control circuit

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A 22nm, 10.8 μ W/15.1 μ W Dual Computing Modes High Power-Performance-Area Efficiency Domained Background Noise Aware Keyword- Spotting Processor

Deep neural network accelerator based on hybrid precision storage

Keyword recognition system based on hybrid compression convolutional neural network

Selection method for calculating bit width of multi-bit-width PE array and calculation precision control circuit