Analysis of critical thermal issues in 3D integrated circuits

3-D chips rely on massive interconnect structures, i.e., large groups of through-silicon vias coalesced with large multibit buses. We observe that wirelength optimization, a classical technique for floorplanning, is not effective while planning massive interconnects. This is due to the interconnects’ strong impact on multiple design criteria like wirelength, routability, and temperature. To facilitate early design progress of massively-interconnected 3-D chips, we propose a novel 3-D-floorplanning methodology which accounts for different types of interconnects in a unified manner. One key idea is to align cores/blocks simultaneously within and across dies, thus increasing the likelihood of successfully implementing complex and massive interconnects. While planning such interconnects, we also target fast, yet accurate, thermal management, routability, and fixed-outline floorplanning. Experimental results on Gigascale Systems Research Center and IBM-HB+ circuits demonstrate our tool’s capabilities for both planning massive 3-D interconnects and for multiobjective 3-D floorplanning in general.

Planning Massive Interconnects in 3-D Chips

Clock tree embedding for 3D ICs

Fast thermal analysis for fixed-outline 3D floorplanning

3D thermal-aware floorplanner using a MOEA approximation

A novel thermal optimization flow using incremental floorplanning for 3D ICs

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A novel thermal optimization flow using incremental floorplanning for 3D ICs