Abstract Hole spins in Ge/SiGe heterostructures have emerged as an interesting qubit platform with favourable properties such as fast electrical control and noise-resilient operation at sweet spots. However, commonly observed gate-induced electrostatic disorder, drifts, and hysteresis hinder reproducible tune-up of SiGe-based quantum dot arrays. Here, we study Hall bar and quantum dot devices fabricated on Ge/SiGe heterostructures and present a consistent model for the origin of gate hysteresis and its impact on transport metrics and charge noise. As we push the accumulation voltages more negative, we observe non-monotonous changes in the low-density transport metrics, attributed to the induced gradual filling of a spatially varying density of charge traps at the SiGe-oxide interface. With each gate voltage push, we find local activation of a transient low-frequency charge noise component that completely vanishes again after 30 hours. Our results highlight the resilience of the SiGe material platform to interface-trap-induced disorder and noise and pave the way for reproducible tuning of larger multi-dot systems. 

pdf/impact-of-interface-traps-on-charge-noise-and-low-density-9upd743e5hw1.pdf

Impact of interface traps on charge noise and low-density transport properties in Ge/SiGe heterostructures

The exploration of multi-gate-controlled electron transport characteristics is always a research focus in Si-based device development and optimization. In this work, we report individual and dual gate-controlled energy band regulations of 30 nm-thick Si membrane and the resulted electron transportations at 10–300 K. It is discovered that the fine energy band structure is a key element to determine electron transport behaviors in fully-depleted silicon-on-insulator. Furthermore, either the front or the back gate bias can modify the energy band bending and sub-band gap, change charged body distribution and intersub-band transition probability, and thus adjust electron mobility and device performance. This dual gate coupling effect together with the proposed gate-controlled sub-band structure model is confirmed by magnetotransport experiments at 1.6 K. Notably, our work presents the coupled gate controlling effects within ultrathin Si film, and gives a physical insight into electron structure modulating, which may promote the evolution of Si-based device applications in many domains.

Electron transport characteristics in dual gate-controlled 30 nm-thick silicon membrane

Exploring the cryogenic transport properties of two-dimensional electron gas in semiconductor heterostructures is always a focus of fundamental research on Si-based gate-controlled quantum devices. In this work, based on the electrical and magnetic transport characteristics of Si/SiGe heterostructure Hall bar-shaped field effect transistors (FETs) at 10 K and 1.6 K, we study the effects of electron tunneling, which occurs in the heterostructure and populates the oxide/semiconductor interface, on its transport properties. The initial position of dual-channel conduction is determined by the gate-controlled electrical hysteresis curves. Furthermore, we discover that there exist different tunneling mechanisms of electrons in a Si quantum well under the action of gate voltage, and the electron tunneling can well explain the two drain current plateaus appearing in direct-current transfer characteristics. Combining the power-law exponent of electron mobility versus density curve and the gate-related Dingle ratio, we clarify the dominant scattering mechanism, and the result can be supported by different tunneling mechanisms. Our work demonstrates the gate-dependent electronic transport performance in undoped Si/SiGe heterostructure FETs, which has an implication for the development of Si/SiGe heterostructure gate-defined quantum dot quantum computation.

Gate-controlled hysteresis curves and dual-channel conductivity in an undoped Si/SiGe 2DEG structure

Quantum computing is expected to break the computing power bottleneck with the help of quantum superposition and quantum entanglement. In order to fabricate fault-tolerant quantum computers for encoding quantum information, it is important to improve the cryogenic mobility of silicon-based metal oxide semiconductor field effect transistors (MOSFETs) with a thin gate dielectric layer as much as possible. Based on a thin SiO2/HfO2 stacked dielectric, we investigate the effect of post-deposition annealing (PDA) temperature on the MOSFET cryogenic transport properties. The results show that silicon atoms will diffuse into the HfO2 to form silicates during PDA, leading to the HfO2 dielectric constant decrease. As the PDA temperature increases, the proportion of monoclinic hafnium oxide decreases and the tetragonal phase increases gradually. The oxygen vacancy content increases gradually, resulting in fixed charge density increases and the mobility decreases. The contribution of the forming gas annealing (FGA) to the mobility enhancement is clarified and the HfO2 recrystallization process is revealed from the perspective of long-time annealing. Finally, the mobility peak of silicon MOSFETs with thin SiO2/HfO2 dielectrics is enhanced to 1387 cm2(V·s)−1 at 1.6 K, which provides a technical pathway for the development of silicon-based quantum computation.

Effect of high temperature annealing on cryogenic transport properties of silicon MOSFETs with a thin SiO2/HfO2 stacked dielectric

Thermal budget is a vital element of Si-based superlattice material processing. In this work, a novel n-type ohmic contact scheme with a low thermal budget process is developed by combining high-dose ion implantation and low-temperature alloying techniques. The optimized specific contact resistivity (ρ c) is reduced to 6.18 × 10−3 Ω cm2 at a low thermal budget of 400 °C, and this is a result of the efficient low-temperature electrical activation of amorphous substances. It is indicated that both the high doping concentration and the formation of a NiSi(Ge) alloy phase contribute to the linear ohmic contact behavior. The ohmic contact resistance dependence on processing temperature is further revealed by a detailed Ni/Si(Ge)alloying model. A minimum ρ c of 2.51 × 10−4 Ω cm2 is achieved at a thermal budget of 450 °C, which is related to the high bonding intensity at the metal–semiconductor interface. Note that this technique is compatible with standard Si-based CMOS process flows and can be applied in high-performance insulated-gate field-effect transistor (IGFET) fabrication. Furthermore, it is verified that the Si/Ge superlattice structures in our IGFETs can serve as an efficient potential barrier to constrain electrons.

Low-thermal-budget n-type ohmic contacts for ultrathin Si/Ge superlattice materials

Cryogenic mobility enhancement, corres- ponding to the reduction of interfacial disorder, is always a research focus in Si-based MOS device manufacturing toward practical quantum computing chips. In this work, we report the dependency of MOSFET cryogenic mobility on reactive ion etching (RIE)-induced damages at 5–75 K. We discover that RIE will introduce a lot of atomic steps and charged traps at SiO2/Si interfaces or conducting channel boundaries during the mesa formation stage, severely degrading device mobility, especially at a low temperature. With a post-RIE high-temperature SiO2 regrowth process, the device cryogenic (1.8 K) peak mobility is enhanced to ~20314 cm2/(<inline-formula> <tex-math notation="LaTeX">$Vs$ </tex-math></inline-formula>) at a small electron density of <inline-formula> <tex-math notation="LaTeX">$1.05\times10$ </tex-math></inline-formula>12/cm2, meaning the successful removal of RIE-induced extra effective scattering centers within the optimized device. Notably, our work presents the adverse impacts of RIE on MOS device cryogenic mobilities and provides a feasible integration flow to recover device performances, which may promote the evolution of Si-based MOS quantum dot computation.

Cryogenic Mobility Enhancement in Si MOS Devices via SiO2 Regrowth

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Cryogenic Mobility Enhancement in Si MOS Devices via SiO2 Regrowth

Gate-controlled hysteresis curves and dual-channel conductivity in an undoped Si/SiGe 2DEG structure