algorithmics and modular computations, Theory of Codes and Cryptography (3).From an analytical 1. RE Blahut. Theory and practice of error control codes. eecs.uottawa.ca/∼yongacog/courses/coding/ (3) R.E. Blahut,Theory and Practice of Error Control Codes, Addison Wesley, 1983. QA 268. Cached. Download as a PDF 457, Theory and Practice of Error Control CodesBlahut 1984 (Show Context). Citation Context..ontinued fractions.

Theory and practice of error control codes

Reed-Solomon (RS) coders are used for error-control coding in many applications such as digital audio, digital TV, software radio, CD players, and wireless and satellite communications. Traditionally, RS coders have been implemented using dedicated hardware. This paper considers software-based implementation of RS codecs. A hardware-software codesign approach is used to design the finite field datapath in a domain-specific digital signal processor (DSP) with low-energy RS codecs application in mind. These datapaths are designed to accommodate programmability with respect to the primitive polynomial as well as the field degree m. A novel heterogeneous digit-serial approach is proposed, where the heterogeneity corresponds to the use of different digit sizes in the multiply-accumulate (MAC) and degree reduction (DEGRED) subarrays. The salient feature of this digit-serial approach is that only the digit cells are implemented in hardware and the finite field multiplications are performed digit-serially in software by dynamically scheduling the internal digit-level operations. Efficient scheduling strategies for digit-serial finite field multiplications are presented and applied to the design of low-energy high-performance RS codecs in software. Significant energy and energy-latency reductions can be achieved using the digit-serial datapaths, as compared with the traditional approach where a combined MAC-DEGRED (parallel multiplier) unit is used. It is concluded that for two-error-correcting RS(n, k) codes over finite field GF(2/sup 8/), datapath containing a parallel MAC unit (of digit size eight) and a DEGRED unit with digit size two (or four) leads to RS codecs with the least energy consumption and energy-latency products; with these datapath architectures and appropriate digit-serial scheduling strategies, more than 60% energy reduction and more than one-third energy-latency reduction can be achieved compared with the parallel multiplication datapath-based approach.

Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecs

This paper presents hardware/software codesign of low-energy programmable Reed-Solomon (RS) codecs. These universal RS(n, k) codecs are to be implemented as a combination of hardware and software in application-specific DSP processors with specially designed programmable finite field datapath and dedicated and optimized software to reduce the total energy consumption. A novel frequency-domain RS decoding procedure using division-free Berlekamp-Massey algorithm is presented. Universal RS decoders are coded using this decoding algorithm as well as other frequency-domain and time-domain decoding schemes based on three types of datapath architectures. From extensive experimental results and cross-comparisons of both energy and energy-latency products, it is concluded that RS decoders using the proposed frequency-domain RS decoding procedure with division-free Berlekamp-Massey algorithm based on finite field datapath with separate MAC and DEGRED units have the best performance.

Low-energy software Reed-Solomon codecs using specialized finite field datapath and division-free Berlekamp-Massey algorithm

The major concerns of VLSI designers in the past were performance, area, reliability and cost. Power was only a secondary issue. In recent years, however, power, area, and speed have become equally important. There are many reasons for this new trend. Primarily, rapid advancement in semiconductor technology over the past decade has enabled designers to integrate many digital CMOS circuits on a single chip. However, the desirability of using these circuits in portable operations has necessitated the development of low-power technology. Portable applications range from desktop computers and audio-video based multimedia products to personal digital assistants and personal communicators. These systems demand both complex functionality and low power, which make their design challenging. The hierarchical energy analysis tool lets designers quickly estimate power consumption of various data-path architectures, enabling a power consumption comparison at a high level before the layout design is carried out.

Power estimation of digital data paths using HEAT

This paper considers implementation of finite field multiplication data paths in a domain-specific programmable digital signal processor (DS-PDSP), where special hardware units and corresponding instructions are assumed to be used to program finite field multiplication operation. These multiplication data paths are designed to accommodate programmability with respect to the primitive polynomial as well as the field order. Three types of multipliers are considered; these include semi-systolic array (in both least-significant-bit first and most-significant-bit first modes), fully-parallel, and the proposed approach where polynomial multiplication and polynomial module operations are implemented separately and two instructions, MAC and DEGRGD are assigned to them, respectively. Two approaches are considered for achieving programmability with respect to the field order, either with special control circuitry, or with pre- and post-logical shifting operations. It is concluded that the one-level pipelined fully-parallel multiplier without control circuitry consumes the least energy at component level when only one multiplication is considered. However, at system level, when vector-vector multiplications, common in most DSP algorithms, are considered, the proposed approach is able to achieve 70% energy reduction at the expense of increasing the total instruction count by one.

Low-energy programmable finite field data path architectures

Reed-Solomon (RS) codecs are used for error control coding in many applications such as digital audio, digital TV, software radio, CD players, and wireless and satellite communications. This paper considers software-based implementation of RS codecs where special instructions are assumed to be used to program finite field multiplication datapaths inside a domain-specific programmable digital-signal processor (DS-PDSP). A heterogeneous digit-serial approach is presented, where the heterogeneity corresponds to the use of different digit-sizes in the multiply-accumulate (MAC for polynomial multiplication) and degree reduction (DEGRED for polynomial module operation) subarrays. The salient feature of this digit-serial approach is that only the digit-cells are implemented in hardware, the finite field multiplications are performed digit-serially in software by dynamically scheduling the internal digit-level operations in RS encoders and decoders. It is concluded that, for 2-error-correcting RS(n,k) codec implementations over finite field GF(2/sup 8/), a parallel MAC unit (of digit-size 8) and a DEGRED unit with digit-size 2 is the best datapath, with respect to least energy consumption and energy-delay products. With this datapath architecture and appropriate digit-serial scheduling strategies, more than 60% energy reduction and more than 1/3 energy delay reduction can be achieved compared with the parallel multiplication datapath based approach.

Low-energy heterogeneous digit-serial Reed-Solomon codecs

This paper presents a low-area finite field divider using dual basis representation. This divider is based on the division algorithm of solving Discrete Wiener-Hopf Equation using Gauss-Jordan elimination method. The hardware complexity of the matrix generation part has been reduced dramatically form O(m/sup 2/) to O(m). When it is used as a building block for a large system, this divider can achieve more savings in hardware by utilizing sub-structure sharing techniques.

Low-area dual basis divider over GF(2/sup M/)

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Low-energy heterogeneous digit-serial Reed-Solomon codecs

Low-area dual basis divider over GF(2/sup M/)