The aim of this paper is to present an approach that allows the generation of VHDL from system level specifications in SDL. Our approach overcomes the main known problem encountered by previous work, which is the communication between different processes. We allow SDL communication to be translated into VHDL for synthesis. This is made possible by the use of an intermediate form that supports a powerful communication model which enables the representation in a synthesis oriented manner of most communication schemes. This intermediate form allows the refinement of the system in order to obtain the desired solution. The main refinement step, called communication synthesis, is aimed at fixing the protocol and the interface used by the different processes to communicate. The refined specification is translated into VHDL for synthesis using existing CAD tools. We illustrate the feasibility of our approach through two SDL to VHDL translation examples.

/pdf/vhdl-generation-from-sdl-specifications-2zv3kjmdrx.pdf

VHDL generation from SDL specifications

Formal methods for software development have been discussed for decades. This paper will try to explain when and under what circumstances formal methods and languages in general and the Object Constraint Language (OCL) in particular can be employed in a beneficial way. The success of using a formal approach is highly influenced by the expectations and pre-requisite knowledge of the developers, the role the formal support in the development process is given, and of course by the used tools.

Reliable Software Technologies - Ada-Europe 2004

This work presents Petri nets as an intermediate model for hardware/software codesign The main reason of using of Petri nets is to provide a model that allows for formal qualitative and quantitative analysis in order to perform hardware/software partitioning Petri nets as an intermediate model allows one to analyze properties of the specification and formally compute performance indices which are used in the partitioning process This paper highlights methods of computing load balance, mutual exclusion degree and communication cost of behavioral description in order to perform the initial allocation and the partitioning This work is also devoted to describing a method for estimating hardware area, and it also presents an overview of the general partitioning method considering multiple software components

http://dz5.pl/ti/Materialy/A%20Petri%20Net%20Model%20For%20Hardware-Software%20Codesign.pdf

A Petri Net Model for Hardware/Software Codesign

Specifications of data computations may not necessarily describe the ranges of the intermediate results that can be generated. However, such information is critical to determine the bit-widths of the resources required for a data-path implementation. In this paper, we present a novel approach based on interval computations that provides, not only guaranteed range estimates that take into account dependencies between variables, but estimates of their probability density functions that can be used when some truncation must be performed due to constraints in the specification. Results show that interval-based estimates are obtained in reasonable times and are more accurate than those provided by independent range computation, thus leading to substantial reductions in area and latency of the corresponding data-path implementation.

/pdf/bit-width-selection-for-data-path-implementations-2kgh8nw0lm.pdf

Bit-width selection for data-path implementations

Embedded systems typically include reactive and transformative functions, often described in different languages and semantics which are well introduced in the various application fields. A large part of the system functionality and components are reused from previous designs including legacy code. There is little hope that a single language will replace this heterogeneous set of languages. A hardware/software codesign process must be able to bridge the semantic differences for verification and synthesis and should accept limited knowledge of system properties. This paper presents the SPI model, which is based on intervals of system properties and is specifically targeted to cosynthesis. This model is the basis of a workbench which is currently under construction in an international cooperation.

Hardware/software codesign of embedded systems the SPI workbench

This paper presents a methodology for hardware-software co-design. It is based on the formal description technique LOTOS in the specification phase, and on estimation methods at different levels of abstraction in the partitioning phase. The LOTOS specification describes the system as a set of interacting communicating processes. Our HW-SW partitioning algorithm is guided by communications, performance and area estimates and by the suitability of each process for implementation in hardware or software. A partition is evaluated against the design goals and constraints, first using high-level estimates and then if requirements are met, computing estimates at lower levels of abstraction. If the partition fails, the partitioning model is updated with the new, low-level estimates and a new partition is generated. If it succeeds, the resulting hardware and software specifications are synthesized using existing high-level synthesis tools and compilers.

A co-design methodology based on formal specification and high-level estimation

A new formal method for the specification, of real-time system requirements and their refinement to a design architecture is set out here. This integrated method is derived from a recently developed formal semantics, logic and refinement calculus for the IEEE standard hardware specification language VHDL. The specification format consists of three-phase "before, during and after" logical schemas, and comes with a combinatorial schema calculus and a refinement theory. The look and feel is reminiscent of Z and VDM and is intended to present an "upgrade path" to real-time for users with specification skills in these languages.

A formal method for specification and refinement of real-time systems

The aim of this document is to present a hardware-software co-design methodology, working through a case study of an Ethernet bridge. This co-design process starts with a system level specification based on the LOTOS formal description technique. The hardware-software partitioning approach is characterized by coarse granularity, a clustering algorithm and a cost function based on estimates at different abstraction levels. Validation accompanies each design stage.

Co-Design at Work: the Ethernet Bridge Case Study

A refinement calculus for the specification of real-time systems and their refinement to a VHDL behavioural description is set out here. The specification format is a logical triple with the look of a Z or VDM schema. Choices from a short menu of refinement operations gradually convert an initial specification to VHDL code through a series of mixed mode intermediates. The calculus is complete in the sense that if there is a code of the VHDL subset considered here (unit-delay waits and signal assignments but no delta delays) satisfying the specification, then it can be obtained by applying some sequence of the refinement operations. The result is "correct by construction".

A refinement calculus for VHDL

The aim of this document is to present a hardware-software co-design methodology, working through a case study of an Ethernet bridge. This co-design process starts with a system level specification based on the LOTOS formal description technique. The hardware-software partitioning approach is characterized by coarse granularity, a

Co-design at work:

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