Intra-cell interference management is one of the technical challenges for device-to-device (D2D) communication underlaying cellular networks. In this paper, we propose two superposition coding-based cooperative relaying schemes to exploit the transmission opportunities for the D2D users without deteriorating the performance of the cellular users. In the first scheme, the D2D transmitter (DT) is enabled to decode and regenerate the cellular signal, and transmit the cellular signal by superposing it with its own signal. In this way, the interference from the D2D pair to the cellular pair can be canceled by properly allocating time and power. To further exploit the transmission opportunity for the D2D pair, in the second scheme the cellular transmitter splits its signal into two parts and broadcasts these two parts in a superposition signal. DT relays only one part of the cellular signal. Analytic and numerical results confirm the efficiency of the proposed schemes.

Cooperative relaying schemes for device-to-device communication underlaying cellular networks

Crossbar-based resistive RAM has been widely used in deep learning accelerator designs because it largely eliminates weight movement between memory and processing units. The high-density storage and low leakage power make it a good fit for edge/IoT devices. However, existing ReRAM designs for traditional neural networks cannot support Attention-based Neural Networks, which are stacked with encoders and decoders instead of convolutional layers or fully connected layers. In addition to matrix-matrix multiplications in traditional neural networks, an encoder or a decoder also includes the attention mechanism, the layer normalization and the gaussian error linear unit. These new characteristics make the data flow far more complicated than that of a convolutional layer. Faulty ReRAM devices are additional obstacles when mapping weights that severely degrade computation accuracy. Existing hardware redundancy strategies that are unaware of application characteristics usually result in inefficient designs. In this work, we analyze the data flow of these attention-based neural networks and propose a ReRAM-based accelerator with a dedicated pipeline design for Attention-based Neural Networks. When considering cells with hard faults in crossbars, we further propose NuXG, a non-uniform redundancy strategy, to meet accuracy requirements and save energy consumption by decreasing the redundancy ratio. Finally, we evaluate results and demonstrate that the proposed can achieve more than two times improved performance over existing redundancy schemes in both power efficiency and throughput for Attention-based Neural Networks. Moreover, it also significantly outperforms an NVIDIA GPU.

ATT: A Fault-Tolerant ReRAM Accelerator for Attention-based Neural Networks

Cognitive Radio is a promising technology for solving spectrum scarcity problem. Design of medium access control (MAC) protocols for Cognitive Radio Networks (CRN) is challenging due to the complexity involved in sensing and accessing the channel. Assuming Primary Users (PUs) to be passive, protocols based on 802.11 MAC has been proposed in the literature. In this paper, we propose a Cognitive Radio MAC protocol for Active primary users (CRMA) and compare it with the existing Cognitive Radio MAC protocol for Passive primary users (CRMP). Unlike CRMP, in the CRMA protocol PUs are assumed to be active, in the sense that PUs are aware of the SUs. PUs signal their intention to transmit over the channel through beacons before transmitting. This minimal change in the functionality of the PUs not only improves the spectrum utilization of the SUs but also decreases the interference to PUs. The performance of both the protocols are compared in terms of throughput, delay, interference to PUs, number of RTS collisions and number of dropped packets of SUs through extensive simulation. We also investigate the effect of packet length, transmission opportunity (TXOP) duration and block acknowledgement. Simulation results show that our proposed CRMA protocol gives better performance as compared to CRMP under certain conditions.

MAC protocols for Cognitive Radio Networks with passive and Active primary users

Quantum computation has taken over as one of the largest current research areas in computer architecture and information theory. With the potential to make a large number of factorization-based encryption methods obsolete, companies and governments around the globe are racing to build the first large-scale quantum computer. Currently, most quantum computers are noisy intermediate-scale quantum (NISQ), using a relatively small collection of unreliable qubits. While error correction methods exist, they require a large number of ancilla qubits to protect the data qubits which is not practical for use on current NISQ machines. However, following the Dowling-Neven Law, available qubits on a superconducting chip are growing at an exponential rate similar to Moore’s Law. Looking toward larger scale quantum machines, we examine a method to increase usable qubit density of quantum machines implementing error correction by using quantum caches that utilize simpler error correction codes. Alternatively, this also allows for the design of reliable systems while meeting the performance and qubit requirements for quantum algorithms. We modify the Qiskit quantum simulation library to work with caches and investigate the effects of region size and topology on the swap characteristics of algorithm execution. We also present our results and discuss recommended topologies for each algorithm. Lastly, we present mix scale-out simulations to examine the impact of cache on future large-scale machines. The default central cache topology gains a maximum performance increase of 2.15 times compared to the worst topology, which creates a robust cache-aware quantum processor layout.

Robust Cache-Aware Quantum Processor Layout

/pdf/performance-and-power-comparisons-between-fermi-and-cypress-4lpqcggq31.pdf

Performance and power comparisons between Fermi and Cypress GPUs

Soft errors have been significantly degrading the reliability of current processors whose feature sizes and supply voltages are fast scaling down. In this paper, we propose two effective approaches to characterize processor reliability against soft errors at pre-silicon stage. By utilizing a rule search strategy named Patient Rule Induction Method (PRIM), we are capable of generating a set of selective rules on key design parameters. These rules quantify the design space subregion with the lowest effective soft error rate (SER), thus providing useful guidelines in designing reliable processors. Furthermore, we also propose to use Classification and Regression Trees (CART) to partition the design space into a number of small subregions each being associated with a representative SER value. This gives the processor designer a global view of the SER distribution, enabling a comprehensive analysis over the entire design space. More importantly, both approaches generate "universal" models whose effectiveness is validated with a set of test programs unseen to training. Compared to traditional application- specific design space studies, our models' cross-program capability can save great training effort in the era of multithreading. Finally, a case study on multiprocessors is performed to simultaneously balance multiple design metrics, including reliability, performance, and power. Index Terms—Hardware reliability, modeling and prediction, modeling of computer architecture. ——————————  ——————————

Comprehensive and Efficient Design Parameter Selection for Soft Error Resilient Processors via Universal Rules Lide Duan, Ying Zhang, Bin Li, and Lu Peng, Member, IEEE Computer Society

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Comprehensive and Efficient Design Parameter Selection for Soft Error Resilient Processors via Universal Rules Lide Duan, Ying Zhang, Bin Li, and Lu Peng, Member, IEEE Computer Society