http://www.norbertwiener.umd.edu/Research/Duhamel_Vetterli_FFT_90.pdf

Fast fourier transforms: a tutorial review and a state of the art

Note: V. K. Madisetti, D. B. Williams, Eds. Reference LCAV-CHAPTER-2005-009 Record created on 2005-06-27, modified on 2017-05-12

Fast Fourier transforms: a tutorial review and a state of the art

A new N = 2n fast Fourier transform algorithm is presented, which has fewer multiplications and additions than radix 2n, n = 1, 2, 3 algorithms, has the same number of multiplications as the Raderi-Brenner algorithm, but much fewer additions, and is numerically better conditioned, and is performed ‘in place’ by a repetitive use of a ‘butterfly’-type structure.

`Split radix' FFT algorithm

A new algorithm is presented for the fast computation of the discrete Fourier transform. This algorithm belongs to that class of recently proposed 2n-FFT's which present the same arithmetic complexity (the lowest among any previously published one). Moreover, this algorithm has the advantage of being performed "in-place," by repetitive use of a "butterfly"-type structure, without any data reordering inside the algorithm. Furthermore, it can easily be applied to real and real-symmetric data with reduced arithmetic complexity by removing all redundancy in the algorithm.

Implementation of "Split-radix" FFT algorithms for complex, real, and real-symmetric data

A fast radix-2 two dimensional discrete cosine transform (DCT) is presented. First, the mapping into a 2-D discrete Fourier transform (DFT) of a real signal is improved. Then an usual polynomial transform approach is used in order to map the 2-D DFT into a reduced size 2-D DFT and one dimensional odd DFT's. Finally, optimized odd DFT algorithms for real signals are developped. All together, a reduction of more than 50% in the number of multiplications and a comparable amount of additions is obtained in comparison to other algorithm.

/pdf/fast-2-d-discrete-cosine-transform-264wic122q.pdf

Fast 2-D discrete cosine transform

Optimal use of high-speed programmable digital signal processors generally demands familiarity with machine architectural features and hence, production of programs whose structure reflects and exploits those features. In contrast, it is apparent that little effort has been made to develop programming techniques which fully realize the signal processing computational capability of standard minicomputers. In this paper, it is shown that a functional high-level language signal processing program can easily be modified so as to produce a similar program which, when executed, automatically generates another program containing precomputed algorithm sequencing and data access information. The generated program will then utilize central processor arithmetic and logical capability only for data-dependent computation. In this way, instructions normally associated with computation for program sequencing/control or data access are eliminated, and all benefits of increased algorithm complexity for reduction of data-dependent arithmetic computation are in fact realized as decreased program execution time. Examples are given of Fortran programs which generate Fortran FFT subroutines and, for completeness, assembly language realizations of the Pfeifer/Blankinship autocorrelation algorithm. Results demonstrate that, using this technique, standard minicomputers may execute digital signal processing algorithms faster than peripheral processors which normally require standard minicomputers as host processors.

Automatic generation of time efficient digital signal processing software

Selection of appropriate algorithms for pitch and formant extraction, in conjunction with use of innovative programming techniques, enables these speech-related features to be derived in real-time on a low-power TMS 320C10 based-system using about 60% of that chip's computing power. Moreover, since LPC-based techniques are used, an accurate low-bit-rate model of the vocal system is inherent in the raw parameters extracted. This programmable system thus provides a flexible foundation for exploring the utility of other fundamental speech features in addition to pitch and formants for excitation of a cochlear prosthesis.

Algorithm selection and software time/Space optimization for a DSP micro-based speech processor for a multi-electrode cochlear implant

The U. S. Naval Research Laboratories algorithm of Elovitz et. al. enables automatic transalation of English text to IPA and, via a further mapping, to input for a "phoneme" based synthesizer such as VOTRAX. A novel feature of the NRL algorithm is that the set of 300+ rules used to perform the translation is read in at run time and thus may be easily altered to expand the set of rules in general or to treat special cases such as jargon. While the orignal NRL FASBOL version ran about 4 to 5 times real time on a PDP-10, Broihier and Crowley implelemented a BASIC Plus version which translated up to 165 words per minute on a PDP-11/70. The program included here consists essentially of a FORTRAN control structure with calls to string manipulation subroutines, available as efficient library routines under the PDP-11 RT-11 operating system. The software runs in less than real time on an LSI-11 with 16K of memory. Alternatively, using the string manipulation routine definitions provided, an all-FORTRAN version may be written. Finally, the straightforward, non-recursive structure employed can implemented in other high level languages. In fact, a PL/M version has been written which, using calls to assembler routines employing block move instructions, will run real time on a Zilog Z-80.

A fast FORTRAN implementation of the U. S. naval research laboratory algorithm for automatic translation of english text to VOTRAX parameters

The nearly simultaneous introduction of DSP (TMS 320) and gp (the J-11 "PDP-11/70-on-a-chip") microcomputers, both with 20 MHz clock rates and 200 nsec add/subtract times allows us to compare similar implementations of different architectures for various DSP benchmarks. We also compare the 320 to a "future" J-11 in which the addition of a 16×16-bit, 200 nsec array multiplier makes the two micromachines "identical" in terms of apparent raw processing power. The conclusions are that although the TMS 320 is a cultural descendent of the PDP-11, the TI machine has at least two significant architectural innovations which account for its enhanced processing speed relative to the PDP-11. These attributes are the use of the barrel shifter in time-transparently scaling data and the need for programmer look-ahead in register-based data addressing. The benchmark programs used to examine the relative machine efficiencies include windowing, autocorrelation, complex-to-magnitude conversion, lattice speech synthesis, and the FFT.

A tale of two architectures: TI TMS 320 SPC vs. DEC Micro/J-11

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Papers

Automatic generation of time efficient digital signal processing software

Automatic generation of time efficient digital signal processing software

Algorithm selection and software time/Space optimization for a DSP micro-based speech processor for a multi-electrode cochlear implant

A fast FORTRAN implementation of the U. S. naval research laboratory algorithm for automatic translation of english text to VOTRAX parameters

A tale of two architectures: TI TMS 320 SPC vs. DEC Micro/J-11