L. Hebert
Freescale Semiconductor
7 Papers
171 Citations
L. Hebert is an academic researcher from Freescale Semiconductor. The author has contributed to research in topics: Gate dielectric & MOSFET. The author has an hindex of 5, co-authored 7 publications.
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Papers
Fermi level pinning at the polySi/metal oxide interface
Chris Hobbs,L. R. C. Fonseca,V. Dhandapani,S. Samavedam,B. Taylor,John M. Grant,L. Dip,Dina H. Triyoso,Rama I. Hegde,David Gilmer,R. Garcia,D. Roan,L. Lovejoy,R. Rai,L. Hebert,H.-H. Tseng,Bruce E. White,Philip J. Tobin +17 more
- 10 Jun 2003
TL;DR: In this article, the first time that Fermi pinning at the polySi/metal oxide interface causes high threshold voltages in MOSFET devices was reported. But the authors did not consider the effect of the interfacial Si-Hf and Si-O-Al bonds.
154
Ultra-thin decoupled plasma nitridation (DPN) oxynitride gate dielectric for 80-nm advanced technology
Hsing-Huang Tseng,Yongjoo Jeon,P. Abramowitz,T. Y. Luo,L. Hebert,J.J. Lee,J. Jiang,Philip J. Tobin,G.C.-F. Yeap,M. Moosa,John R. Alvis,S.G.H. Anderson,N. Cave,T.C. Chua,Andreas Hegedus,G. Miner,J. Jeon,A. Sultan +17 more
TL;DR: In this paper, the nitrogen profile of DPN gate dielectric can be engineered primarily by tuning the plasma pressure after optimizing other DPN process parameters to solve the non-optimal nitrogen profile in the film.
48
•Proceedings Article
Metal gate MOSFETs with HfO2 gate dielectric
S. Samavedam,H.-H. Tseng,Philip J. Tobin,J. Mogab,S. Dakshina-Murthy,L. B. La,J. A. Smith,J. Schaeffer,M. Zavala,Ryan Martin,Bich-Yen Nguyen,L. Hebert,O. Adetutu,V. Dhandapani,T-Y. Luo,R. Garcia,P. Abramowitz,M. Moosa,David Gilmer,Chris Hobbs,W. Taylor,John M. Grant,Rama I. Hegde,S. Bagchi,E. Luckowski,V. Arunachalam,M. Azrak +26 more
- 01 Jan 2002
TL;DR: In this paper, the first time electrical characterization of HfO 2 p- and n-MOSFETs with CVD TiN and PVD TaSiN gates respectively fabricated using conventional CMOS integration was reported.
16
Metal gate MOSFETs with HfO/sub 2/ gate dielectric
S. Samavedam,H.-H. Tseng,Philip J. Tobin,J. Mogab,S. Dakshina-Murthy,L. B. La,J. A. Smith,J. Schaeffer,M. Zavala,Ryan Martin,Bich-Yen Nguyen,L. Hebert,O. Adetutu,V. Dhandapani,T. Y. Luo,R. Garcia,P. Abramowitz,M. Moosa,David Gilmer,Chris Hobbs,W. Taylor,John M. Grant,Rama I. Hegde,S. Bagchi,E. Luckowski,V. Arunachalam,M. Azrak +26 more
- 11 Jun 2002
TL;DR: In this article, the first time electrical characterization of HfO/sub 2/ p- and n-MOSFETs with CVD TiN and PVD TaSiN gates respectively fabricated using conventional CMOS integration was reported.
10
Threshold voltage instability and plasma induced damage of polySi/HfO/sub 2/ devices - positive impact of deuterium incorporation
H.-H. Tseng,M. Ramon,L. Hebert,Philip J. Tobin,Dina H. Triyoso,S. Kalpat,John M. Grant,Z.X. Jiang,David C. Gilmer,D. Menke,W.J. Taylor,Olubunmi O. Adetutu,Bruce E. White +12 more
- 04 Oct 2004
TL;DR: In this paper, deuterium was incorporated during the ALD process to improve the interface quality that enhances high-K device stability and reliability, resulting in a significantly smaller voltage shift after constant voltage stressing at room temperature and at 125/spl deg/C under NBTI/PBTI conditions, as well as a longer CHCI lifetime.
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