The fabrication of transistors using vertical, six-sided core–multishell indium gallium arsenide nanowires with an all-surrounding gate on a silicon substrate combines the advantages of a three-dimensional gate architecture with the high electron mobility of the III–V nanowires, drastically enhancing the on-state current and transconductance. In the continuing drive to improve and miniaturize transistors, the microelectronics industry has recently adopted three-dimensional electronic gate structures. Another way of improving transistors is to use semiconductor materials with higher electron mobility than silicon, although this presents significant fabrication challenges. Katsuhiro Tomioka et al. combine the two approaches; they grow, with high precision, vertical, six-sided core–multishell indium gallium arsenide nanowires with an all-surrounding gate on a silicon substrate. The resulting devices demonstrate superior transistor performance with excellent on/off switching behaviour and fast operation. Silicon transistors are expected to have new gate architectures, channel materials and switching mechanisms in ten years’ time1,2,3,4. The trend in transistor scaling has already led to a change in gate structure from two dimensions to three, used in fin field-effect transistors, to avoid problems inherent in miniaturization such as high off-state leakage current and the short-channel effect. At present, planar and fin architectures using III–V materials, specifically InGaAs, are being explored as alternative fast channels on silicon5,6,7,8,9 because of their high electron mobility and high-quality interface with gate dielectrics10. The idea of surrounding-gate transistors11, in which the gate is wrapped around a nanowire channel to provide the best possible electrostatic gate control, using InGaAs channels on silicon, however, has been less well investigated12,13 because of difficulties in integrating free-standing InGaAs nanostructures on silicon. Here we report the position-controlled growth of vertical InGaAs nanowires on silicon without any buffering technique and demonstrate surrounding-gate transistors using InGaAs nanowires and InGaAs/InP/InAlAs/InGaAs core–multishell nanowires as channels. Surrounding-gate transistors using core–multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability. These devices provide a route to making vertically oriented transistors for the next generation of field-effect transistors and may be useful as building blocks for wireless networks on silicon platforms.

A III–V nanowire channel on silicon for high-performance vertical transistors

High-conductivity two-dimensional electron gases at AlN∕GaN heterojunctions are reported. The sheet densities can be tuned from ∼5×1012∕cm2to∼5×1013∕cm2 by varying the AlN thickness from 2to7nm. A critical thickness is observed beyond which biaxial strain relaxation and cracking of AlN occur, and a degradation of carrier mobility is seen to occur at extremely high sheet densities. A high-mobility window is identified, within which room-temperature mobility exceeding 1000cm2∕Vs. and sheet densities in the (1–3)×1013∕cm2 are obtained, yielding record low sheet resistances in the range of ∼170Ω∕◻. Interface roughness scattering and strain relaxation are identified as the factors preventing lower sheet resistances at present.

High-mobility window for two-dimensional electron gases at ultrathin AlN∕GaN heterojunctions

The hole mobility of $p$-type strained Si metal-oxide-semiconductor field-effect transistors (MOSFET's) fabricated on a SiGe substrate is investigated theoretically and compared with the mobility of conventional (unstrained) Si $p$-MOSFET's. Two-dimensional quantization of the holes is taken into account in terms of a self-consistent six-band $\mathbf{k}\mathbf{\ensuremath{\cdot}}\mathbf{p}$ model for the strained band structure and the confined hole subband states in the inversion channel. The hole dynamics along the inversion channel is studied in terms of ensemble Monte Carlo calculations that take into account all relevant scattering mechanisms. For a Ge concentration of $30%$ in the substrate, we predict a mobility enhancement of a factor of 2.3 compared to the unstrained $p$-type device. The calculated low-field mobility is in excellent agreement with experimental data for strained ${\mathrm{S}\mathrm{i}/\mathrm{S}\mathrm{i}}_{0.8}{\mathrm{Ge}}_{0.2}$ and for unstrained Si $p$-MOSFET's.

Subband structure and mobility of two-dimensional holes in strained Si/SiGe MOSFET’s

A method for the fabrication of nonpolar indium gallium nitride (InGaN) films as well as nonpolar InGaN-containing device structures using metalorganic chemical vapor deposition (MOVCD). The method is used to fabricate nonpolar InGaN/GaN violet and near-ultraviolet light emitting diodes and laser diodes.

Fabrication of nonpolar indium gallium nitride thin films, heterostructures and devices by metalorganic chemical vapor deposition

InAs/GaSb nanowire heterostructures with thin GaInAs inserts were grown by MOVPE and characterized by electrical measurements and transmission electron microscopy. Down-scaling of the insert thickness was limited because of an observed sensitivity of GaSb nanowire growth to the presence of In. By employing growth interrupts in between the InAs and GaInAs growth steps it was possible to reach an insert thickness down to 25 nm. Two-terminal devices show a diode behavior, where temperature-dependent measurements indicate a heterostructure barrier height of 0.5 eV, which is identified as the valence band offset between the InAs and GaSb. Three-terminal transistor structures with a top-gate positioned at the heterointerface show clear indications of band-to-band tunnelling.

InAs/GaSb Heterostructure Nanowires for Tunnel Field-Effect Transistors

A self‐consistent, one‐dimensional solution of the Schrodinger and Poisson equations is obtained using the finite‐difference method with a nonuniform mesh size. The use of the proper matrix transformation allows preservation of the symmetry of the discretized Schrodinger equation, even with the use of a nonuniform mesh size, therefore reducing the computation time. This method is very efficient in finding eigenstates extending over relatively large spatial areas without loss of accuracy. For confirmation of the accuracy of this method, a comparison is made with the exactly calculated eigenstates of GaAs/AlGaAs rectangular wells. An example of the solution of the conduction band and the electron density distribution of a single‐heterostructure GaAs/AlGaAs is also presented.

A self-consistent solution of Schrödinger-Poisson equations using a nonuniform mesh

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A self-consistent solution of Schrödinger-Poisson equations using a nonuniform mesh