A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread switch will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive unproductive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.

Altering thread priorities in a multithreaded processor

A system and method for performing computer processing operations in a data processing system includes a multithreaded processor (110) and thread switch logic (400) The multithreaded processor (110) is capable of switching between two or more threads of instructions which can be independently executed Each thread has a corresponding state in a thread state register (440) depending on its execution status The thread switch logic contains a thread switch control register (410) to store the conditions upon which a thread switch can occur Upon the occurrence of a thread switch event, the state and priority of all threads are dynamically interrogated to determine which thread should be the active thread executing the processor The thread switch logic has a time-out register (430) which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time Thread switch logic also has a forward progress count register (420) to prevent repetitive unproductive thread switching between threads in the multithreaded processor Thread switch logic also is responsive to a thread switch manager (460) capable of changing the priority of the different threads and thus superseding thread switch events

Thread switch control in a multithreaded processor system

A cluster architecture for a highly parallel multiprocessor computer processing system (40) is comprised of one or more clusters of tightly-coupled, high-speed processors (10) capable of both vector and scalar parallel processing that can symmetrically access shared resources (12) associated with the cluster, as well as the shared resources associated with other clusters.

Cluster architecture for a highly parallel scalar/vector multiprocessor system

A co-processor resource manager allocates resources of a co-processor platform to nodes implementing operations requested by applications running on a host processor according to a user-modifiable prioritization of the operations. Lower priority nodes can be evicted by the manager to resolve resource conflicts for newly requested operations. The manager utilizes a query test for the platform driver or client to override eviction or prevent eviction by downgrading an operation's resource usage. A platform driver tracks resource usage of nodes, and classifies resources as singly allocatable or countable types to maintain co-processor resource manager independence from the co-processor platform.

Prioritized co-processor resource manager and method

A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.

Method and apparatus to force a thread switch in a multithreaded processor

A micro-program controlled data processing system having a plurality of data processors integrally formed within a central processor unit for performing on a priority assigned time slice basis a plurality of data processing functions Dedicated registers within the central processor unit are functionally grouped and connected to share common resource main storage, control storage and shared register circuits The functional groups of dedicated registers when activated to share the common resource circuits, define a plurality of data processors The processors execute machine language instruction programs under micro-program control wherein each processor when active performs a unique data processing task functionally independent of the other processors A resource allocation circuit selectively activates the individual processors on a minute time slice basis, where a time slice has approximately the same time duration as the storage reference time of the data processor system, such that one or more micro-program instruction is executed by the active processor during each time slice The resource allocation circuit successively activates processors in a manner such that processor activation switching is accomplished with zero central processor unit overhead The resource allocation circuit includes a priority network that receives real time common resource utilization requests from the processors according to the individual processor''s needs, assigns a priority rating to the received requests and alters in response thereto the otherwise sequential activation of the processors Program execution efficiency of each processor is thereby maximized, and individual processors appear to be simultaneously continuously executing their associated machine language programs

Multi-processor data processing system

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Multi-processor data processing system