Clocked comparators have found widespread use in noise sensitive applications including analog-to-digital converters, wireline receivers, and memory bit-line detectors. However, their nonlinear, time-varying dynamics resulting in discrete output levels have discouraged the use of traditional linear time-invariant (LTI) small-signal analysis and noise simulation techniques. This paper describes a linear, time-varying (LTV) model of clock comparators that can accurately predict the decision error probability without resorting to more general stochastic system models. The LTV analysis framework in conjunction with the linear, periodically time-varying (LPTV) simulation algorithms available from RF circuit simulators can provide insights into the intrinsic sampling and decision operations of clock comparators and the major contribution sources to random decision errors. Two comparators are simulated and compared with laboratory measurements. A 90-nm CMOS comparator is measured to have an equivalent input-referred random noise of 0.73 mVrms for dc inputs, matching simulation results with a short channel excess noise factor ? = 2.

Simulation and Analysis of Random Decision Errors in Clocked Comparators

A deep understanding of how to reduce flicker phase noise (PN) in oscillators is critical in supporting ultra-low PN frequency generation for the advanced communications and other emerging high-speed applications. Unfortunately, the current literature is either full of conflicting theories and ambiguities or too complex in mathematics, hiding the physical insights. In this brief, we comprehensively review the evolution of flicker noise upconversion theories and clarify their controversial and confusing parts. Two classes of such upconversion mechanisms in voltage-biased $LC$ -tank oscillators (nMOS-only and complementary) are specifically compared and numerically verified using a commercial simulation model of 28-nm CMOS. We identify that non-resistive terminations of both 2nd and 3rd harmonic currents contribute to oscillation waveform asymmetries that lead to the flicker noise upconversion. Further, we discuss three $1/f^{3}$ PN reduction mechanisms: waveform shaping, narrowing of conduction angle, and gate-drain phase shift.

Oscillator Flicker Phase Noise: A Tutorial

A power-efficient transmitter is proposed using a multiphase serializer, multiphase dividers using injection-locked oscillators, and a high-speed multiplexing structure to relax the timing constraints. With this architecture, bit times near 1 FO-4 gate delay are achieved using only nominal V
 T 
devices in a 65 nm CMOS technology. The divider and serializer operate over a wide range of data rates between 32 and 48 Gb/s limited mainly by the operation range of the frequency synthesizer. The transmitter occupies 0.4 mm
 2 
and consumes 88 mW from a 1.2 V supply which corresponds to 1.8 pJ/bit of power efficiency.

A 32–48 Gb/s Serializing Transmitter Using Multiphase Serialization in 65 nm CMOS Technology

This brief describes a simple method to compute the impulse sensitivity function (ISF) of oscillators by means of the periodic transfer function analysis that is available in most of the commercial circuit simulators. The proposed calculation method, relying on linear-time variant simulations, is at least an order of magnitude more efficient than a conventional direct computation of the ISF based on transient analysis.

Efficient Calculation of the Impulse Sensitivity Function in Oscillators

Timing jitter is one of the most significant phase-locked loop (PLL) characteristics, which directly affects the performance of the system in which the PLL is used. It is, therefore, important to develop the tools necessary to study and predict PLL jitter performance at design time. In this paper a discrete-time, linear, periodically time-variant integer-N PLL model for jitter analysis is proposed, which accounts for the periodically time-varying effect of noise injected into the loop at various PLL components, such as VCO, charge pump, VCO buffer, VCO control node, and divider. The model also predicts the aliasing of jitter due to the downsampling and upsampling of the jitter signal around the PLL loop. Closed-form expressions are derived for the output jitter spectrum and match well with results of event-driven simulations of a third-order PLL.

/pdf/discrete-time-linear-periodically-time-variant-phase-locked-3ozn9p61gx.pdf

Discrete-Time, Linear Periodically Time-Variant Phase-Locked Loop Model for Jitter Analysis

Impulse sensitivity function analysis of periodic circuits

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Impulse sensitivity function analysis of periodic circuits