Introspection of DNN-Based Perception Functions in Automated Driving Systems: State-of-the-Art and Open Research Challenges

This paper introduces the whole process of verifying the AHB-SRAM controller using UVM verification methodology, and expounds the verification function points, coverage statistics and final regression in the implementation process. The verification results show that the read and write functions of the AHB-SRAM controller under various conditions are correct and its coverage rate reaches 100% in the regression test. his paper is based on UVM verification method, which has high portability, improves the verification efficiency and meets the chip verification requirements.

Function Verification of SRAM Controller Based on UVM

One of the most significant trends in the semiconductor industry is mixed-signal applications. A great amount of effort is focused on creating fast and accurate designs, which include both analog and digital components. As a result, mixed-signal verification poses a major concern. Previous traditional verification techniques offer slow verification time and relatively small robustness. In this work, an efficient UVM-based verification architecture for a digital phase-locked loop (DPLL) real number model using SystemVerilog is presented. The UVM capabilities of the proposed methodology combined with the RNM model of the digital PLL favors the generation of a reusable, time-to-market fast and robust verification environment. Cadence Incisive Enterprise Simulator was used for the testbench creation and simulation. The proposed verification architecture uses constrained-random stimulus generation, analog assertions and coverage metrics, in order to achieve high gains in verification efficiency.

UVM-based Verification of a Digital PLL Using SystemVerilog

Monitoring the state of materials in verification environment for IP architectures using python based verification mechanism

As the SoC complexity is increasing day by day to incorporate more functionalities, verification is also becoming complex and time consuming. To enable faster verification, a structured methodology is required. Universal Verification Methodology (UVM) is one such method consisting of a library of base classes based on SystemVerilog which can be extended for the required functionality. In this paper, an interconnection soft Intellectual Property (IP) used in automobile applications for incorporating complex functionalities is verified efficiently using UVM. The IP is highly programmable and parameterized for wide range of products. The basic metrics of verification, namely, code coverage and functional coverage are achieved in an efficient manner using the methodology. The code coverage was found to be 80.3% and functional coverage was found to be 82.08%.

Verification of Interconnection IP for Automobile Applications using System Verilog and UVM

This paper introduces an extendable and generic base architecture built on Universal Verification Methodology (UVM) for verifying Flash memory controller designs. The base architecture aims to create a generic and configurable abstraction verification environment for Flash memory controller designs. It integrates the essential UVM Verification Components (VCs), defines the functionalities of the VCs, and connects them in a generic and dynamic approach. It also implements some base functions and tasks for Flash memory controller verification environment. In addition, it provides the implementation of the UVM phases' functions and tasks. The configuration mechanism of the base architecture supports the verification of multiple memory controllers and other peripherals. This paper guides the verifier where and how to put the behavior of Flash memory controller in its correct and suitable place in the base architecture to serve the idea of reusability which the UVM originally is built on. This paper introduces a case study of the base verification architecture and provides its experimental result. This paper also introduces a lot of UVM knowledge to make the verifier efficiently exploit this base architecture and reuse it in many other verification projects.

Extendable generic base verification architecture for flash memory controllers based on UVM

In recent years, Neural Networks (NNs) have been widely adopted in engineering automated driving systems with examples in perception, decision-making, or even end-to-end scenarios. As these systems are safety-critical in nature, they are too complex and hard to verify. For using neural networks in safety-critical domains, it is important to know if a decision made by a neural network is supported by prior similarities in the training process. Verifying a trained neural network is to measure the extent of the decisions made by the neural network, which are based on prior similarities in the training process. In this paper, we propose a runtime monitoring that can measure the reliability of the neural network trained to classify a new input based on prior similarities in the training set. In the training process, the runtime monitor stores the values of the neurons of certain layers, which represent the neurons activation pattern for each example in the training data. We use the Binary Decision Diagrams (BDDs) formal technique to store the neuron activation patterns in binary form. In the inference process, a classification decision measured by a hamming distance is made to any new input by examining if the runtime monitor contains a similar neurons activation pattern. If the runtime monitor does not contain any similar activation pattern, it generates a warning that the decision is not based on prior similarities in the training data. Unlike previous work, we monitored more layers to allow for more neurons activation pattern of each input. We demonstrate our approach using the MNIST benchmark set. Our experimental results show that by adjusting the hamming distance, 75.63% of the misclassified labels are unseen activation patterns, which are not similar to any stored activation patterns from the training time.

Verification of Neural Networks for Safety Critical Applications

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Extendable generic base verification architecture for flash memory controllers based on UVM

Verification of Neural Networks for Safety Critical Applications