After two decades of research and development, elliptic curve cryptography now has widespread exposure and acceptance. Industry, banking, and government standards are in place to facilitate extensive deployment of this efficient public-key mechanism. Anchored by a comprehensive treatment of the practical aspects of elliptic curve cryptography (ECC), this guide explains the basic mathematics, describes state-of-the-art implementation methods, and presents standardized protocols for public-key encryption, digital signatures, and key establishment. In addition, the book addresses some issues that arise in software and hardware implementation, as well as side-channel attacks and countermeasures. Readers receive the theoretical fundamentals as an underpinning for a wealth of practical and accessible knowledge about efficient application. Features & Benefits: * Breadth of coverage and unified, integrated approach to elliptic curve cryptosystems * Describes important industry and government protocols, such as the FIPS 186-2 standard from the U.S. National Institute for Standards and Technology * Provides full exposition on techniques for efficiently implementing finite-field and elliptic curve arithmetic* Distills complex mathematics and algorithms for easy understanding* Includes useful literature references, a list of algorithms, and appendices on sample parameters, ECC standards, and software toolsThis comprehensive, highly focused reference is a useful and indispensable resource for practitioners, professionals, or researchers in computer science, computer engineering, network design, and network data security.

https://cdn.preterhuman.net/texts/cryptography/Hankerson,%20Menezes,%20Vanstone.%20Guide%20to%20elliptic%20curve%20cryptography%20(Springer,%202004)(ISBN%20038795273X)(332s)_CsCr_.pdf

Guide to Elliptic Curve Cryptography

National Institute of Standards and Technology における超伝導研究及び生活

비만아 부모의 돌봄 경험: q 방법론

In this paper we describe T-MAC, a contention-based Medium Access Control protocol for wireless sensor networks. Applications for these networks have some characteristics (low message rate, insensitivity to latency) that can be exploited to reduce energy consumption by introducing an activesleep duty cycle. To handle load variations in time and location T-MAC introduces an adaptive duty cycle in a novel way: by dynamically ending the active part of it. This reduces the amount of energy wasted on idle listening, in which nodes wait for potentially incoming messages, while still maintaining a reasonable throughput.We discuss the design of T-MAC, and provide a head-to-head comparison with classic CSMA (no duty cycle) and S-MAC (fixed duty cycle) through extensive simulations. Under homogeneous load, T-MAC and S-MAC achieve similar reductions in energy consumption (up to 98%) compared to CSMA. In a sample scenario with variable load, however, T-MAC outperforms S-MAC by a factor of 5. Preliminary energy-consumption measurements provide insight into the internal workings of the T-MAC protocol.

/pdf/an-adaptive-energy-efficient-mac-protocol-for-wireless-12upticrf7.pdf

An adaptive energy-efficient MAC protocol for wireless sensor networks

Most of the signal processing that we will study in this course involves local operations on a signal, namely transforming the signal by applying linear combinations of values in the neighborhood of each sample point. You are familiar with such operations from Calculus, namely, taking derivatives and you are also familiar with this from optics namely blurring a signal. We will be looking at sampled signals only. Let's start with a few basic examples. Local difference Suppose we have a 1D image and we take the local difference of intensities, DI(x) = 1 2 (I(x + 1) − I(x − 1)) which give a discrete approximation to a partial derivative. (We compute this for each x in the image.) What is the effect of such a transformation? One key idea is that such a derivative would be useful for marking positions where the intensity changes. Such a change is called an edge. It is important to detect edges in images because they often mark locations at which object properties change. These can include changes in illumination along a surface due to a shadow boundary, or a material (pigment) change, or a change in depth as when one object ends and another begins. The computational problem of finding intensity edges in images is called edge detection. We could look for positions at which DI(x) has a large negative or positive value. Large positive values indicate an edge that goes from low to high intensity, and large negative values indicate an edge that goes from high to low intensity. Example Suppose the image consists of a single (slightly sloped) edge:

http://ieeexplore.ieee.org/iel5/5/31307/01456462.pdf

Linear systems

The complex valued matched filter correlators consume maximum power in the DS/SS CDMA receivers. These correlators accumulate 1024 samples lying in the range -7 to +7. This accumulation needs 3 data bits, 1 sign bit and 10 extra bits for overflow. Hence, the correlator can be implemented as a cascade of 4-bit full adder and a 10-bit incrementer. As a ripple carry adder (RCA) consumes the least power among all the existing adder architectures, we have implemented the 4-bit adder as a RCA. Previous incrementers were implemented as ripple counters. In this paper we propose a novel incrementer which is faster than a ripple counter based incrementer. Hence, it can be operated at a reduced voltage resulting in considerable power reduction. The incrementer is implemented using multiplexers, AND gates and TSPC registers. The ripple-counter correlator and the proposed incrementer correlator were laid out in MAGIC using 0.5µ CMOS technology followed by power estimation using HSPICE. It is shown that the proposed architecture requires 50% less power than a ripple counter based design.

/pdf/a-low-power-correlator-444kavdwck.pdf

A low-power correlator

This paper presents a low-area finite field divider using dual basis representation. This divider is based on the division algorithm of solving Discrete Wiener-Hopf Equation using Gauss-Jordan elimination method. The hardware complexity of the matrix generation part has been reduced dramatically form O(m/sup 2/) to O(m). When it is used as a building block for a large system, this divider can achieve more savings in hardware by utilizing sub-structure sharing techniques.

Low-area dual basis divider over GF(2/sup M/)

Backpropagation Computation for Training Graph Attention Networks

Chemical reaction networks (CRNs) provide a fundamental model in the study of molecular systems. Widely used as formalism for the analysis of chemical and biochemical systems, CRNs have received renewed attention as a model for molecular computation. This paper demonstrates that, with a new encoding, CRNs can compute any set of polynomial functions subject only to the limitation that these functions must map the unit interval to itself. These polynomials can be expressed as linear combinations of Bernstein basis polynomials with positive coefficients less than or equal to 1. In the proposed encoding approach, each variable is represented using two molecular types: a type-0 and a type-1. The value is the ratio of the concentration of type-1 molecules to the sum of the concentrations of type-0 and type-1 molecules. The proposed encoding naturally exploits the expansion of a power-form polynomial into a Bernstein polynomials. The method is illustrated first for generic CRNs; then the chemical reactions designed for two examples are mapped to DNA strand-displacement reactions.

Computing Polynomials by Chemical Reaction Networks

The average power consumption is proportional to the average value of transition activity, i.e., transition probability, and the variance of transition activity determines the strength of power grid noise. In this paper, for the first time, a simple accurate model for estimating the variance of transition activity was proposed, and the dual bit type (DBT) model for estimating the average transit ion activity was further developed. Tile model for estimating transition activity variance is based on linearly modeling the spatial correlation of bit-level transition activity, which leads to low computational complexity for computing the variance with very good estimation accuracy. The previous DBT model is made complete with the equation derived in this paper for computing the transition probabili ty beyond the breakpoint BP~. In addition to DSP computational architecture and algorithm designs, the proposed simple models are of great significance for power grid noise decoupling and chip floor-planning designs. 1. I N T R O D U C T I O N Over the past few years, the low-power design issues have received much attention mostly due to the emergence of mobile applications, where the average power consumption determines the lifetime of a battery. The average power consumption also plays an important role on the reliability and the packaging cost of high performance ICs, such as microprocessors which consume large power in order to run at high clock fi-equency. As semi-conductor technology moves rapidly into deep submicron (DSM) stage, the design challenge for delivering reliable ICs becomes more severe due to very low supply voltage, shrinked wire width and much tighter noise margin constraints. Therefore, in DSM technology, tile knowledge of the average power consumption *This research was supported by Defense Advanced Research Project Agency under contract number DA/DABT63-96-C-0050 Permission to make digital or hard copies of all or part of this work tbr personal or classroom use is granted without Ibc provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific pcmaission and/or a t?e. GLSVLS12001 West Lafayette. Indiana. USA Copyright ACM 2001 1-58113-351-0/01/03...$5-00 121 alone is not sufficient for designing a reliable IC. Both tile peak power consumption and the power grid noise have a heavy weight in design process. These two new factors can cause the malfunction of a digital circuit or the performance degradation of an analog circuit in a mixed signal IC chip, which prevents a system-on-chip (SOC) design from being implemented. From this viewpoint, the accurate knowledge and control of the average power consumption, the peak power consumption and tile power grid noise are crucial for successful chip designs. For CMOS circuits, there are three types of power consumption, i.e., static (or leakage), short circuit and dynamic (or switching). The switching power consumption arises when an output node makes a voltage transition from low to high, which is usually from 0V to power supply Vdd [1], and can be represented as P(n) = a(n)CL V~dfclk (1) where P(n) is the power consumption at clock cycle n; o~(n) is the transition activity [2][3] at clock cycle n, whose value is 1 for transit ion (0 to 1) or 0 otherwise; CL is the capacitance load at the output. The average switching power is the average value of equation (1) with respect to ca(n) and can be represented as 2 P = caCLVddfcl k (2), where ca = E[a(n)] , referred as transition probability in [2][3], and ca(n) is assumed stationary. The values of capacitance load of circuits can be extracted using the method presented in [2][3]. To obtain the values of transition probability a for general logic circuits, it requires comprehensive simulations for input vector space. However, for DSP datapaths and components, the values of ca can be more readily computed from signal statistical properties. In [2][3], the relationship between transit ion probabili ty and signal statistics was provided as the dual bit type (DBT) model. In [4][5], more treatments of this issue were presented, where the bit-level lag-1 temporal correlation is modeled instead, and the transition probabil i ty is computed from the bit-level temporal correlation and the bit-level probability. However, in [4][5], a complex procedure using signal probability density function (pd~ is required to compute the bit-level probability. In spite of above aspects, none of these three approaches address the second order statistical properties of transition activity, which determine the magnitude of power grid noise. In this paper, the DBT model is further developed and a forPermission to make digital or hard copies of part or all of this work or personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers, or to redistribute to lists, requires prior sp cific permission and/or a fee. GLSVLSI 2001, est afayette, Indiana, S © ACM 2001 1-58113-351-0/00/03...$5.0 mula for computing the transition probability beyond breakpoint BPz is derived. Thereafter, the proposed model for computing power grid noise is presented. In this paper, all discussions axe limited to datapath situations because up to 40% of the total power may be dissipated in buses, drivers and multiplexors [6]. For components, the transition activity will be larger than that of datapaths due to glitching [5] and this problem can be solved separately. The remainder of this paper has four sections. In section 2, the DBT model is summarized and the augmentation to it is presented. In section 3, a linear model for characterizing the spatial correlation of bit-level transition activity is proposed to compute the variance of transition activity and thus the power grid noise. In section, 4, the information about inStantaneous and peak power consul,nptions are illustrated using transition activity distribution plots. Section 5 is the conclusion of this work. 2. AVERAGE TRANSITION ACTIVITY The first part of this section serves as a summary of the DBT model presented in [2][3]. The remaining part shows the augmentation to the DBT model, which makes the DBT model complete. 2.1 Preliminaries For a stationary signal x(n) with mean value of # = E[x(n)], its vaxiance 0 -2 is given by 0 2 = E [ ( x ( n ) #)2] = E[x~(n) ] _ #2 (3) and its lag-1 temporal correlation p is defined as: E[(x(n) # ) ( x ( n 1) #)] p = E[(x(n) ~)2] E[~(~0x(n 1 ) ] #~ = 0-2 (4) The square-root of variance, 0-, is referred as staxl,daxd deviat ion of the signal. When the signal x(n) is represented as a B-bit binary vector ( xBl , (n ) , . ' ' , xl (n), x0(n)), the quantity ai(n), given by ai(n) = xi(n 1)zi(n), (5) is referred as bit-level transition activity of i-th bit, and the quantity A(n), given by

/pdf/models-for-power-consumption-and-power-grid-noise-due-to-3lbwh7nu8p.pdf

Models for power consumption and power grid noise due to datapath transition activity

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