Keshab K. Parhi
University of Minnesota
777 Papers
8.1K Citations
Keshab K. Parhi is an academic researcher from University of Minnesota. The author has contributed to research in topics: Computer science & Decoding methods. The author has an hindex of 68, co-authored 749 publications. Previous affiliations of Keshab K. Parhi include University of California, Berkeley & University of Warwick.
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Papers
Low-Energy Architectures of Linear Classifiers for IoT Applications using Incremental Precision and Multi-Level Classification
Sandhya Koteshwara,Keshab K. Parhi +1 more
- 30 May 2018
TL;DR: This paper presents a novel incremental-precision classification approach that leads to a reduction in energy consumption of linear classifiers for IoT applications and a novel data-path decomposition is proposed to design of fixed-width adders and multipliers.
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Angle-constrained IIR filter pipelining for reduced coefficient sensitivities
TL;DR: In this paper, an angle-constrained filter design approach using a modified Remez exchange algorithm is proposed to avoid tight pole-crowding in pipelined filters by scattered lookahead.
3
Patent
Fast and small serial huffman decoder for decoding at an optimally high rate
Robert Allen Freking,Keshab K. Parhi +1 more
- 15 Mar 2000
TL;DR: In this article, a serial Huffman decoder that is concise and capable of extremely high rates of operation is described, and optimal speed is attained because the critical-path of an embodying circuit has only a memory in the critical path.
3
Static and dynamic information derived from source and system features for person recognition from humming
TL;DR: H hum of a person is used to design a voice biometric system for person recognition and a recently proposed static feature set, viz., Variable length Teager energy based Mel Frequency Cepstral Coefficients (VTMFCC), is found to capture source-like information of a hum signal.
3
Patent
Pipelined add-compare-select circuits and methods, and applications thereof
Keshab K. Parhi
- 13 Dec 2002
TL;DR: In this article, the add-compare-select circuits include logic segments separated by delay devices, and the separation of the logic segments allows for pipelining of the addcompare select processes and advantageous circuit retiming.
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