Kenzo Hatada
4 Papers
38 Citations
Kenzo Hatada is an academic researcher. The author has contributed to research in topics: Flip chip & Thermal copper pillar bump. The author has an hindex of 2, co-authored 4 publications.
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Papers
Patent
Semiconductor chip and method manufacturing the same
R Ogaki Enomoto,Hideo Yabashi,Tadashi Ogaki-kita-kojou Sugiyama,Kenzo Hatada +3 more
- 30 Mar 2001
TL;DR: A via 42 is formed by copper plating on a surface of an aluminum electrode pad 32 of a semiconductor chip 30. Since the via 42 having flexibility absorbs a stress generated due to a difference in thermal expansion between the semiconductor chips 30 and a substrate, the semiconduct chip 30 can be mounted onto the substrate 50 with high reliability and connection reliability of the semicode chip 30 as discussed by the authors.
33
Patent
Semiconductor chip with bump contacts
R Ogaki Enomoto,Hideo Yabashi,Tadashi Ogaki-kita-kojou Sugiyama,Kenzo Hatada +3 more
- 27 Sep 1999
TL;DR: An aluminum electrode pad (32) of a semiconductor chip (30) is plated with copper to form a via (42), which is so flexible as to absorb the stress produced by the difference in thermal expansion between the semiconductor chips and its substrate.
5
Patent
Semiconductor chip and manufacture method thereof
R Ogaki Enomoto,Hideo Yabashi,Tadashi Ogaki-kita-kojou Sugiyama,Kenzo Hatada +3 more
- 27 Sep 1999
TL;DR: An aluminum electrode pad (32) of a semiconductor chip (30) is plated with copper to form a via (42), which is so flexible as to absorb the stress produced by the difference in thermal expansion between the semiconductor chips and its substrate.
Patent
Semiconductor chip and semiconductor chip manufacturing method
R Ogaki Enomoto,Hideo Yabashi,Tadashi Ogaki-kita-kojou Sugiyama,Kenzo Hatada +3 more
- 27 Sep 1999
TL;DR: A via 42 is formed by copper plating on a surface of an aluminum electrode pad 32 of a semiconductor chip 30. Since the via 42 having flexibility absorbs a stress generated due to a difference in thermal expansion between the semiconductor chips 30 and a substrate, the SIC can be mounted onto the substrate 50 with high reliability and connection reliability of the chip 30 can be enhanced.