Modern transmission line theory and applications

This paper presents an overview of the physics, modeling, and circuit implications of RF broad-band noise, low-frequency noise, and oscillator phase noise in SiGe heterojunction bipolar transistor (HBT) RF technology. The ability to simultaneously achieve high cutoff frequency (f/sub T/), low base resistance (r/sub b/), and high current gain (/spl beta/) using Si processing underlies the low levels of low-frequency 1/f noise, RF noise, and phase noise of SiGe HBTs. We first examine the RF noise sources in SiGe HBTs and the RF noise parameters as a function of SiGe profile design, transistor biasing, sizing, and operating frequency, and then show a low-noise amplifier design example to bridge the gap between device and circuit level understandings. We then examine the low-frequency noise in SiGe HBTs and develop a methodology to determine the highest tolerable low-frequency 1/f noise for a given RF application. The upconversion of 1/f noise, base resistance thermal noise, and shot noises to phase noise is examined using circuit simulations, which show that the phase noise corner frequency in SiGe HBT oscillators is typically much smaller than the 1/f corner frequency measured under dc biasing. The implications of SiGe profile design, transistor sizing, biasing, and technology scaling are examined for all three types of noises.

Noise in SiGe HBT RF Technology: Physics, Modeling, and Circuit Implications

Historically speaking, the world of extremely low-noise solid-state amplification has been dominated by exotic technologies such as InP and GaAs HEMTs. By cryogenically cooling these devices, it is possible to realize microwave amplifiers with noise temperatures as low as 5K over decades of bandwidth. Although HEMTs can provide very low noise amplification when cooled to cryogenic temperatures, their radiometer performance is limited by intrinsic transconductance fluctuations. It is believed that bipolar devices do not suffer from this problem. As industry has invested more and more money into silicon based technologies, silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) have continued to improve and are now at the point where they are beginning to become competitive with InP HEMTs for microwave cryogenic low-noise amplifiers. Although extremely high frequency device operation has been observed at cryogenic temperatures, little work has been done on modeling the noise of cooled SiGe HBTs. In this report, a thorough investigation into the theoretical and practical aspects of using silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) for extremely low-noise applications is presented. The dissertation is broken up into three sections: 1) Background information: The fundamentals of SiGe HBTs are presented along with a discussion of how the properties of semiconductors change at cryogenic temperatures, as well the impact that these changes have on the performance of the devices. 2) Modeling: A comprehensive study of seven state-of-the-art HBTs at temperatures ranging from 18 K to 300 K is presented. The devices are compared in terms of dc, small-signal, and noise performance, and small-signal noise models are extracted. The section concludes with a brief summary of the important conclusions regarding the performance of SiGe devices at cryogenic temperatures. 3) Applications: The models developed previously are applied to the design of several state-of-the-art LNAs in both MMIC and discrete form. Noise performance better than 2 K is achieved in the low-GHz range, which is comparable to the best InP results. The section concludes with a discussion of some high-impedance differential amplifiers which have recently been fabricated.

Silicon-Germanium Heterojunction Bipolar Transistors for Extremely Low-Noise Applications

This paper presents a general 4-port algorithm that can remove on-wafer parasitics from on-wafer measurements after impedance standard substrate (ISS) calibration of system errors, or remove both system errors and on-wafer parasitics in a single step without ISS calibration. On-wafer standards are fabricated on a 0.13 RF CMOS process, and experimental data are measured from 2 to 110 GHz using an HP 8510XF system. The impact of nonideal on-wafer load standards is examined using the deembedded transistor-parameters and the extracted small signal parameters. The errors remaining after the traditional open-short deembedding are numerically evaluated, which become significant above 50 GHz. The solved 4-port network for on-wafer parasitics is indeed reciprocal despite the assumptions of ideal OPEN and SHORT, thus allowing a mathematically simpler reciprocal 4-port solution. The general 4-port solution can also be directly applied to the measured raw S-parameters to remove both system errors and on-wafer parasitics in a single step. Single-step calibration leads to reasonably accurate transistor -parameters, despite the less accurate on-wafer standards compared to precision ISS standards.

A General 4-Port Solution for 110 GHz On-Wafer Transistor Measurements With or Without Impedance Standard Substrate (ISS) Calibration

This paper compares on-wafer thru-reflect-line (TRL) and off-wafer short-open-load-thru (SOLT) and line-reflect-reflect-match (LRRM) vector-network-analyzer probe-tip calibrations for amplifier characterization and parasitic-extraction calibrations for transistor characterization on silicon integrated circuits at millimeter-wave frequencies We show that on-wafer calibrations generally outperform off-wafer and LRRM probe-tip calibrations at millimeter-wave frequencies However, certain parasitic-extraction algorithms designed specifically to remove contact pads, transmission-lines, and access vias correct for much of the error in off-wafer calibrations

Calibrations for Millimeter-Wave Silicon Transistor Characterization

This paper presents modeling of correlated RF noise in the intrinsic base and collector currents of SiGe heterojunction bipolar transistors using quasi-static equivalent circuits. The noises are first extracted from measured noise parameters using standard noise circuit analysis. Using the extraction results, model equations are proposed to describe both the frequency and bias dependence of the correlated noise sources using a single set of model parameters. The model is demonstrated using noise data from both measurement and microscopic noise simulation. The model is shown to work at frequencies up to at least half of the peak f/sub T/ and at biasing currents below high injection f/sub T/ rolloff.

Frequency and bias-dependent modeling of correlated base and collector current RF noise in SiGe HBTs using quasi-static equivalent circuit

A new approach to implementing correlated high-frequency noise in bipolar junction transistor (BJT) large-signal compact models is developed by placing an RC -delayed noise current between the base and collector nodes. The approach reproduces the two stages of noise transport in a BJT, i.e., noise generation in the base and emitter and transportation through the collector-base junction space-charge region (CB SCR). The frequency dependence of the intrinsic noise sources due to the CB SCR is fully described with an accuracy value up to the second order of ω. As an example, the negative frequency dependence of Sic is correctly described for the first time. The approach is applicable to any large-signal compact model, and it is demonstrated using measurement data in both InGaP/GaAs heterojunction bipolar transistors (HBTs) and SiGe HBTs.

A New Approach to Implementing High-Frequency Correlated Noise for Bipolar Transistor Compact Modeling

This paper presents an improved algorithm to solve the general 4-port parasitics de-embedding problem. Experimental results on 0.13 mum RF CMOS device are presented. For the device examined, gate resistance extracted from open-short results is 40% lower than that extracted from 4-port results. The reciprocity and symmetry of the 4-port parasitics are also examined

An Improved On-chip 4-Port Parasitics De-embedding Method with Application to RF CMOS

This article presents PSPHV, a surface-potential-based compact model for laterally diffused MOS (LDMOS) transistors. PSPHV includes a new drain voltage scaling technique that enables accurate modeling of saturation in transistors with nonuniform lateral doping; gate bias-dependent interface charge, which models the gradual channel turn- ON seen in devices with halo doping; internal drain bias clamping, which eliminates the capacitance spikes seen in most existing LDMOS models; and a new avalanche current model for the drift region that accounts for the Kirk effect. PSPHV models the drain expansion effect and diode reverse recovery and is verified against experimental data.

PSPHV: A Surface-Potential-Based Model for LDMOS Transistors

The general van Vliet noise model for transistors was derived for base minority carriers only under adiabatic boundary conditions. This paper extends the model by including the emitter minority carrier noise and the base–collector space charge region (CB SCR) effects based on the mathematical framework developed by van Vliet. Both the finite surface recombination velocity at polysilicon emitter and the finite carrier exit velocity at CB SCR are considered. It is proved that the van Vliet model can be directly used to include the emitter minority carrier noise, and the model holds when the two finite velocity boundary conditions are imposed. A new set of equations are derived to include the effect of CB SCR delay on noise.

Discussions and extension of van Vliet’s noise model for high speed bipolar transistors

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