Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (two-dimensional) ICs may not be suitable. This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occurring a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D chip. Furthermore, one of the major concerns in 3-D ICs arising due to power dissipation problems has been analyzed and an analytical model has been presented to estimate the temperatures of the different active layers. It is demonstrated that advancement in heat sinking technology will be necessary in order to extract maximum performance from these chips. Implications of 3-D device architecture on several design issues have also been discussed with special attention to SoC design strategies. Finally some of the promising technologies for manufacturing 3-D ICs have been outlined.

/pdf/3-d-ics-a-novel-chip-design-for-improving-deep-submicrometer-6k9by1rs19.pdf

3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to dramatically enhance chip performance, functionality, and device packing density. They also provide for microchip architecture and may facilitate the integration of heterogeneous materials, devices, and signals. However, before these advantages can be realized, key technology challenges of 3D ICs must be addressed. More specifically, the processes required to build circuits with multiple layers of active devices must be compatible with current state-of-the-art silicon processing technology. These processes must also show manufacturability, i.e., reliability, good yield, maturity, and reasonable cost. To meet these requirements, IBM has introduced a scheme for building 3D ICs based on the layer transfer of functional circuits, and many process and design innovations have been implemented. This paper reviews the process steps and design aspects that were developed at IBM to enable the formation of stacked device layers. Details regarding an optimized layer transfer process are presented, including the descriptions of 1) a glass substrate process to enable through-wafer alignment; 2) oxide fusion bonding and wafer bow compensation methods for improved alignment tolerance during bonding; 3) and a single-damascene patterning and metallization method for the creation of high-aspect-ratio (6:1 108 vias/cm2), and extremely aggressive wafer-to-wafer alignment (submicron) capability.

Three-dimensional integrated circuits

Recently, the development of three-dimensional large-scale integration (3D-LSI) has been accelerated. Its stage has changed from the research level or limited production level to the investigation level with a view to mass production. The 3D-LSI using through-silicon via (TSV) has the simplest structure and is expected to realize a high-performance, high-functionality, and high-density LSI cube. This paper describes the current and future 3D-LSI technologies with TSV.

Through-Silicon Via (TSV)

State-of-the-art image sensors suffer from significant limitations imposed by their very principle of operation. These sensors acquire the visual information as a series of “snapshot” images, recorded at discrete points in time. Visual information gets time quantized at a predetermined frame rate which has no relation to the dynamics present in the scene. Furthermore, each recorded frame conveys the information from all pixels, regardless of whether this information, or a part of it, has changed since the last frame had been acquired. This acquisition method limits the temporal resolution, potentially missing important information, and leads to redundancy in the recorded image data, unnecessarily inflating data rate and volume. Biology is leading the way to a more efficient style of image acquisition. Biological vision systems are driven by events happening within the scene in view, and not, like image sensors, by artificially created timing and control signals. Translating the frameless paradigm of biological vision to artificial imaging systems implies that control over the acquisition of visual information is no longer being imposed externally to an array of pixels but the decision making is transferred to the single pixel that handles its own information individually. In this paper, recent developments in bioinspired, neuromorphic optical sensing and artificial vision are presented and discussed. It is suggested that bioinspired vision systems have the potential to outperform conventional, frame-based vision systems in many application fields and to establish new benchmarks in terms of redundancy suppression and data compression, dynamic range, temporal resolution, and power efficiency. Demanding vision tasks such as real-time 3-D mapping, complex multiobject tracking, or fast visual feedback loops for sensory-motor action, tasks that often pose severe, sometimes insurmountable, challenges to conventional artificial vision systems, are in reach using bioinspired vision sensing and processing techniques.

Retinomorphic event-based vision sensors: Bioinspired cameras with spiking output

A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

System comprising a semiconductor device and structure

We proposed a new three-dimensional (3D) shared memory for a high performance parallel processor system. In order to realize such new 3D shared memory, we have developed a new 3D integration technology based on the wafer stacking method. We fabricated the 3D shared memory test chip with three memory layers using our 3D integration technology. It was demonstrated that the basic memory operation and the broadcast operation of 3D shared memory are successfully performed.

Three-dimensional shared memory fabricated using wafer stacking technology

Information processing in the human brain is based on advanced parallel processing with a large number of memories and interconnections To achieve such highly advanced parallel processing, the human brain has modules with layered structures, that is, three-dimensional structures as basic processing units The human retina and visual cortex also have layered structures with various kinds of cells The three-dimensional (3D) integration technology reported here achieves an image processing and pattern recognition system with parts of functions of the retina and visual cortex using silicon

Neuromorphic vision chip fabricated using three-dimensional integration technology

A new three-dimensional (3D) integration technology for realizing a highly parallel image-processing chip has been developed. Several LSI wafers are vertically stacked and glued to each other after thinning them using this new technology. This technology can be considered as both 3D LSI technology and wafer-scale 3D chip-on-chip packaging technology. The effective packaging density can be significantly increased by stacking the chips in a vertical direction. Several key techniques for this 3D integration have been developed. In this paper, we demonstrate the highly parallel image sensor chip with a 3D structure. The 3D image sensor test chip was fabricated using this new 3D integration technology and its basic performance was evaluated.

https://iopscience.iop.org/article/10.1143/JJAP.39.2473/pdf

Development of Three-Dimensional Integration Technology for Highly Parallel Image-Processing Chip.

Y. Igarashi, T. Morooka, Y. Yamada, T. Nakamura, K.W. Leel, ICT. park, H. Kurino and M. Koyanagr DepL ofMachine lntelligence and Systems Engineering, 'Ibhoku Univ. 0l Aza-Ararnaki, Aoba-ku, Sendei 98G8579, Japan Phone: +81-22-217{909; E-Mail: sdlab(Asd.mech.tohoku.acjp rJST(Japan Science and Technolo$/ Corporation)

Filling of Tungsten into Deep Trench Using Time-Modulation CVD Method

The smart vision chip has a large potential for application in general purpose high speed image processing systems. In order to fabricate smart vision chips including photo detector compactly, we have proposed the application of three dimensional LSI technology for smart vision chips. Three dimensional technology has great potential to realize new neuromorphic systems inspired by not only the biological function but also the biological structure. In this paper, we describe our three dimensional LSI technology for neuromorphic circuits and the design of smart vision chips.

/pdf/smart-vision-chip-fabricated-using-three-dimensional-2e9yevavn2.pdf

Smart Vision Chip Fabricated Using Three Dimensional Integration Technology

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