K. W. Lee
Tohoku University
35 Papers
174 Citations
K. W. Lee is an academic researcher from Tohoku University. The author has contributed to research in topics: Wafer & Chip. The author has an hindex of 9, co-authored 35 publications.
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Papers
Self-assembly technology for reconfigured wafer-to-wafer 3D integration
Takafumi Fukushima,E. Iwata,K. W. Lee,Tetsu Tanaka,Mitsumasa Koyanagi +4 more
- 01 Jun 2010
TL;DR: In this article, a reconfigured wafer-to-wafer 3D integration using surface tension-powered multichip self-assembly and multi-chip transfer techniques was introduced.
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New chip-to-wafer 3D integration technology using hybrid self-assembly and electrostatic temporary bonding
Takafumi Fukushima,H. Hashiguchi,Jichoel Bea,Yoshikazu Ohara,M. Murugesan,K. W. Lee,Tetsu Tanaka,Mitsumasa Koyanagi +7 more
- 01 Dec 2012
TL;DR: In this paper, the authors proposed a new chip-to-wafer 3D integration technology using hybrid self-assembly and electrostatic temporary bonding, which achieved high-throughput chip assembly of above 10,000 chips/hour with a high alignment accuracy of < 1 μm.
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A very low area ADC for 3-D stacked CMOS image processing system
Koji Kiyoyama,K. W. Lee,Takafumi Fukushima,Hideki Naganuma,Harufumi Kobayashi,Tetsu Tanaka,Mitsumasa Koyanagi +6 more
- 16 Aug 2012
TL;DR: A very small circuit area analog-to-digital converter (ADC) for three-dimensional (3-D) stacked CMOS image processing system and the time interleaved charge-redistribution successive approximation (SAR) method is employed.
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Self-assembly technologies with high-precision chip alignment and fine-pitch microbump bonding for advanced die-to-wafer 3D integration
Takafumi Fukushima,Yoshikazu Ohara,M. Murugesan,Jichoel Bea,K. W. Lee,Tetsu Tanaka,Mitsumasa Koyanagi +6 more
- 20 Jun 2011
TL;DR: In this article, surface tension-driven chip self-assembly for 3D stacking of a large number of known good dies (KGDs) on silicon substrates in batch processing was demonstrated.
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Non-conductive film and compression molding technology for self-assembly-based 3D integration
Takafumi Fukushima,Yoshikazu Ohara,Jichoel Bea,M. Murugesan,K. W. Lee,Tetsu Tanaka,Mitsumasa Koyanagi +6 more
- 30 Jul 2012
TL;DR: In this article, two key technologies consisting of chip-to-wafer bonding through a nonconductive film (NCF) and wafer-level packaging using compression molding were studied for self-assembly-based 3D integration, especially reconfigured wafer towafer stacking, where 4mm-by-5mm chips having 20μm-pitch Cu-SnAg microbumps were successfully bonded to wafers through NCF.
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