A dual-k spacer concept is proposed and evaluated in underlap and nonunderlap n-channel silicon tunnel field-effect transistors (FETs) for the first time using extensive device simulations. The dual-k spacer consists of an inner layer made of a high-k material and an outer layer made of a low-k material. It is shown that the dual-k spacer improves the performance of n-channel tunneling FETs and more so for the underlap structures. Performance improvements are illustrated and explained for SiO2, Al2O3, and HfO2 gate dielectrics. The structure is optimized for the on-state current without degrading the off-state current or the subthreshold slope.

Dual- $k$ Spacer Device Architecture for the Improvement of Performance of Silicon n-Channel Tunnel FETs

Effective work-function control technique applicable to p-type FinFET high-k/metal gate devices

Feasibly adjusting the gate leakage and the device performance in balance is an obvious challenge. Additionally, stacking the high-k dielectric as a gate dielectric in nanonode process is an appreciate way to promote the drive current in pMOSFETs. Unfortunately, the amount of oxygen vacancy or the interfacial layer thickness on the surface channel will possibly reduce the drive current owing to the increasing magnitude of threshold voltage and increase in the gate leakage degrading the standby capability in circuit operation. To retard this disadvantage or intensify the device quality, applying a lower pressure decoupled-plasma nitridation process to obliquely reform the amount of oxygen vacancy is a feasible alternative. On the basis of tested data, the nitridation treatment in a higher N
 2
 concentration is better than that in a lower one, such as the improvement of gate leakage, drive current, subthreshold swing, and channel mobility in pMOSFETs, especially for shorter channel-length devices.

Gate Leakage Characteristics for 28 nm HfZrO x pMOSFETs After DPN Process Treatment With Different Nitrogen Concentration

Today’s information age is driven by silicon based electronics. For nearly four decades semiconductor industry has perfected the fabrication process of continuingly scaled transistor – heart of modern day electronics. In future, silicon industry will be more pervasive, whose application will range from ultra-mobile computation to bio-integrated medical electronics. Emergence of flexible electronics opens up interesting opportunities to expand the horizon of electronics industry. However, silicon – industry’s darling material is rigid and brittle. Therefore, we report a generic batch fabrication process to convert nearly any silicon electronics into a flexible one without compromising its (i) performance; (ii) ultra-large-scale-integration complexity to integrate billions of transistors within small areas; (iii) state-of-the-art process compatibility, (iv) advanced materials used in modern semiconductor technology; (v) the most widely used and well-studied low-cost substrate mono-crystalline bulk silicon (100). In our process, we make trenches using anisotropic reactive ion etching (RIE) in the inactive areas (in between the devices) of a silicon substrate (after the devices have been fabricated following the regular CMOS process), followed by a dielectric based spacer formation to protect the sidewall of the trench and then performing an isotropic etch to create caves in silicon. When these caves meet with each other the top portion of the silicon with the devices is ready to be peeled off from the bottom silicon substrate. Release process does not need to use any external support. Released silicon fabric (25 m thick) is mechanically flexible (5 mm bending radius) and the trenches make it semi-transparent (transparency of 7%).

/pdf/mechanically-flexible-optically-transparent-silicon-fabric-54hdnpcqlm.pdf

Mechanically flexible optically transparent silicon fabric with high thermal budget devices from bulk silicon (100)

High-k/metal gate stacks have been introduced in CMOS technology during the last decade in order to sustain continued device scaling and ever-improving circuit performance. Starting from the 45 nm ...

/pdf/integration-of-thulium-silicate-for-enhanced-scalability-of-1t8ijpxt7v.pdf

Integration of thulium silicate for enhanced scalability of high-k/metal gate CMOS technology

A comprehensive materials set has been fabricated and characterized to address the challenging issues in both gate first and gate last HK/MG CMOS. Specifically, metal gate thermal budget and channel composition are shown to be effective methods to engineer pMetal effective work function for gate last and gate first, respectively. Low temperature processing has resulted in low nMOS V fb and high pMOS V fb (ΔEWF=~900mV) without the V fb roll-off typically observed for gate first pMetals. Gate first high-k/metal gate CMOS has also been demonstrated using dual channel, single metal gate. Excellent pFET Ion-Ioff characteristics, 500 µA/µm at 1nA/µm for V dd =1V have been achieved without additional strain engineering owing to: [i] optimized SiGe thickness, [ii] optimized Ge concentration, [iii] reduced R ext , [iv] minimized Coulomb scattering at short channel, and [v] scaled gate oxide thickness.

Alternative approaches for high-k/metal gate CMOS: Low temperature process (gate last) and SiGe channel

This paper reports on a scalable and simple gate-first integration option for manufacturing the high-k/metal gate CMOS transistors targeting sub-32 nm LSTP applications: Vt < plusmn 0.45 V (at Lg = 60 nm) at EOT les 1.4 nm, with 105 times Jg reduction compared to SiO2. This scheme integrates several simplifications and improvements for the first time: single metal gate material, single channel material, dual selective LaOx / AlOx cap removal without lithographic overlay tolerances issues and optimized HfSiON for LSTP leakage targets.

A scalable and highly manufacturable single metal gate/high-k CMOS integration for sub-32nm technology for LSTP applications

This paper presents results on nMOSFETs with the La-doped high-k/metal gate stack to see its suitability for sub-32nm LSTP and HP applications. The 32nm gate length transistors exhibit an excellent I on -I off characteristic, and the PBTI results meet the 32nm technology node requirement. Furthermore, for the first time, V t variation in the La-doped high-k/metal gate stack devices is investigated. The results suggest that employing the metal electrode suppresses V t variability while no additional parameter fluctuations due to La-doping of the high-k dielectric were observed.

La-doped metal/high-K nMOSFET for sub-32nm HP and LSTP application

Handle everyday research tasks with reliable, citation-backed results

Your personal Research Agent to handle research tasks with citation-backed results

Popular Tasks used by Researchers

How can I help with your research?

Meet SciSpace

Get more enhanced response by uploading the PDFs you want me to reference.

No relevant PDFs in your library

SciSpace is the AI research assistant for academics. Run systematic literature reviews on 280M+ papers, and write papers with cited sources. Trusted by 1M+ students, PhDs & researchers.

SciSpace | AI for Research

Analyze PDFs

Code & Manuscripts

Funding & Grants

Literature & Patents

Medical & Clinical Data

Systematic Review

Visualize & Present

Web & Data

Build a Google Scholar-like website for your research.

Build a website

Create charts and images for your research

Create a Chart

Write a paper for submission to a journal

Draft a manuscript

Patent Search

Design eye-catching scientific posters in minutes.

Scientific Poster Generation

Systematic Literature Review

One task is running at the moment. Your messages will be shown right after.

Drag and drop or click here to browse

Loved by <highlight>1 million+</highlight> researchers

Extract a list of specific topics and their sources from unstructured text

Topics

Compare and analyze relevant papers that matches with your search

Papers

Get insights from PDFs and bookmarked papers from your library

My library

Recent searches

Try searching for:

Catch AI-generated content in scholarly and non-scholarly content

{ai} Detector

Ai Writer

Get PDF Summaries, highlighted text explanations 

Chat with PDF

Effortlessly create in-text citations and bibliographies in APA and 2,500 other formats

Citation generator

Get explanations, summaries, and answers on academic papers

Ease up your research workflow with {scispace}'s cohort of exciting AI tools

Elevate your academic writing skills and convey your ideas the way you want

Paraphraser

Explore our range of reading and writing tools

Your file is being prepared and should be ready in a few minutes. If it's a large file, it might take a bit longer. You can close this window, and we'll email you the file when it's done.

You have reached a maximum limit of <strong>{limit}</strong> columns in the table. Remove at least <strong>1</strong> column to add or create another one.

K. Tateiwa

Author Tools

Chat about Author

Papers

Alternative approaches for high-k/metal gate CMOS: Low temperature process (gate last) and SiGe channel

A scalable and highly manufacturable single metal gate/high-k CMOS integration for sub-32nm technology for LSTP applications

La-doped metal/high-K nMOSFET for sub-32nm HP and LSTP application