Storage-class memory (SCM) combines the benefits of a solid-state memory, such as high performance and robustness, with the archival capabilities and low cost of conventional hard-disk magnetic storage. Such a device would require a solid-state nonvolatile memory technology that could be manufactured at an extremely high effective areal density using some combination of sublithographic patterning techniques, multiple bits per cell, and multiple layers of devices. We review the candidate solid-state nonvolatile memory technologies that potentially could be used to construct such an SCM. We discuss evolutionary extensions of conventional flash memory, such as SONOS (silicon-oxide-nitride-oxide-silicon) and nanotraps, as well as a number of revolutionary new memory technologies. We review the capabilities of ferroelectric, magnetic, phase-change, and resistive random-access memories, including perovskites and solid electrolytes, and finally organic and polymeric memory. The potential for practical scaling to ultrahigh effective areal density for each of these candidate technologies is then compared.

Overview of candidate device technologies for storage-class memory

Harnessing the potential of single crystal inorganic nanowires for practical advanced nanoscale applications requires not only reproducible synthesis of highly regular one-dimensional (1D) nanowire arrays directly on device platforms but also elegant device integration which retains structural integrity of the nanowires while significantly reducing or eliminating complex critical processing steps. Here we demonstrate a unique, direct, and bottom-up integration of a semiconductor 1D nanowire, using zinc oxide (ZnO) as an example, to obtain a vertical surround-gate field-effect transistor (VSG-FET). The vertical device structure and bottom-up integration reduce process complexity, compared to conventional top-down approaches. More significantly, scaling of the vertical channel length is lithographically independent and decoupled from the device packing density. A bottom electrical contact to the nanowire is uniquely provided by a heavily doped underlying lattice-match substrate. Based on the nanowire-integrated platform, both n- and p-channel VSG-FETs are fabricated. The vertical device architecture has the potential for use in tera-level ultrahigh-density nanoscale memory and logic devices.

Single Crystal Nanowire Vertical Surround-Gate Field-Effect Transistor

Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.

Ultrahigh density vertical nand memory device and method of making thereof

A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.

Nonvolatile Semiconductor Memory Device

A method of making a monolithic, three dimensional NAND string, includes forming a select transistor, forming a first memory cell over a second memory cell, forming a first word line for the first memory cell, forming a second word line for the second memory cell, forming a bit line, forming a source line, and forming a select gate line for the select transistor. The first and the second word lines are not parallel to the bit line, and the first and the second word lines extend parallel to at least one of the source line and the select gate line.

Method of making three dimensional NAND memory

In order to overcome the limitation of cell area of 4F/sup 2/ per bit in conventional NAND flash memory cells, stacked-surrounding gate transistor (S-SGT) structured cell is proposed. This newly structured cell achieves a cell area of 4F/sup 2//N per bit, where N is the number of stacked memory cells in one silicon pillar, without using multibit per memory cell technology. The S-SGT structured cell consisting of two stacked memory cells in one silicon pillar achieves a cell area per bit of less than 50% of the smallest reported NAND structured cell. The novel S-SGT structured cells are fabricated by vertical self-aligned processes using a 0.2 /spl mu/m design rule. The S-SGT structured cell can be programmed and erased by uniform injection and uniform emission of Fowler-Nordheim (F-N) tunneling electrons over the whole channel area of the memory cell, respectively, which is the same program and erase mechanism as in conventional NAND structured cell. This high performance S-SGT structured cell is applicable to high-density nonvolatile memories for 16 G/64 G bit Flash memories and beyond.

Novel ultra high density flash memory with a stacked-surrounding gate transistor (S-SGT) structured cell

Abstract Cellulose nanofibers (CNFs), which are plant-derived materials, have recently garnered considerable attention owing to their excellent mechanical properties, such as their low weight and high Young’s modulus. Novel methods for producing 100% CNF bulk structural materials have been developed. However, the tribological properties of CNFs have not been investigated thus far although their mechanical properties are known and are comparable to those of some conventional structural materials. In this study, the tribological properties of a novel biomass material, 100% CNF molding, were investigated based on CNF/steel contacts under dry and boundary lubrication conditions at various temperatures. The friction test results showed that the friction coefficient and wear volume of the CNF molding increased with the test temperature of the CNF/steel tribopair under dry-sliding conditions. Conversely, no significant temperature dependence of the friction and wear properties was observed upon lubrication with a pure polyalfaolefin. The surface analytical results revealed that the amorphization of the CNF molding progressed on the worn surface, especially under dry-sliding conditions at a high temperature. All the results suggested that the friction and wear performance of the 100% CNF moldings strongly depends on the sliding test conditions, and the amorphization process of the CNF molding can affect its friction and wear performance. 

Tribological properties of 100% cellulose nanofiber (CNF) molding under dry- and boundary lubrication-conditions at CNF/steel contacts

Digital spatial profiling of the tumor microenvironment in Hodgkin‐like adult T‐cell leukemia/lymphoma

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Novel ultra high density flash memory with a stacked-surrounding gate transistor (S-SGT) structured cell

Tribological properties of 100% cellulose nanofiber (CNF) molding under dry- and boundary lubrication-conditions at CNF/steel contacts

Digital spatial profiling of the tumor microenvironment in Hodgkin‐like adult T‐cell leukemia/lymphoma