In this paper, we propose and validate a novel design for a double-gate tunnel field-effect transistor (DG tunnel FET), for which the simulations show significant improvements compared with single-gate devices using a gate dielectric. For the first time, DG tunnel FET devices, which are using a high-gate dielectric, are explored using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average subthreshold swing of 57 mV/dec, and a minimum point slope of 11 mV/dec. The 2D nature of tunnel FET current flow is studied, demonstrating that the current is not confined to a channel at the gate-dielectric surface. When varying temperature, tunnel FETs with a high-kappa gate dielectric have a smaller threshold voltage shift than those using SiO2, while the subthreshold slope for fixed values of Vg remains nearly unchanged, in contrast with the traditional MOSFET. Moreover, an Ion/Ioff ratio of more than 2 times 1011 is shown for simulated devices with a gate length (over the intrinsic region) of 50 nm, which indicates that the tunnel FET is a promising candidate to achieve better-than-ITRS low-standby-power switch performance.

https://www.silvaco.co.kr/tech_lib_TCAD/simulationstandard/2008/jan_feb_mar/a2/jan-feb-mar08_a2.pdf

Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric

High-k gate dielectrics, particularly Hf-based materials, are likely to be implemented in CMOS advanced technologies. One of the important challenges in integrating these materials is to achieve lifetimes equal or better than their SiO/sub 2/ counterparts. In this paper we review the status of reliability studies of high-k gate dielectrics and try to illustrate it with experimental results. High-k materials show novel reliability phenomena related to the asymmetric gate band structure and the presence of fast and reversible charge. Reliability of high-k structures is influenced both by the interfacial layer as well as the high-k layer. One of the main issues is to understand these new mechanisms in order to asses the lifetime accurately and reduce them.

Review on high-k dielectrics reliability issues

Effect of gate engineering in double-gate MOSFETs for analog/RF applications

A dielectric film containing a nanolaminate with a hafnium oxide layer and a zirconium oxide layer and a method of fabricating such a dielectric film produce a reliable gate dielectric having an equivalent oxide thickness thinner than attainable using silicon oxide.

ATOMIC LAYER DEPOSITED NANOLAMINATES OF HfO2/ZrO2 FILMS AS GATE DIELECTRICS

Electron and hole mobility in HfO/sub 2//metal gate MOSFETs is deeply studied through low-temperature measurements down to 4.2 K. Original technological splits allow the decorrelation of the different scattering mechanisms. It is found that even when charge trapping is negligible, strong remote coulomb scattering (RCS) due to fixed charges or dipoles causes most of the mobility degradation. The effective charges are found to be located in the HfO/sub 2/ near the SiO/sub 2/ interface within 2 nm. Experimental results are well reproduced by RCS calculation using 7/spl times/10/sup 13/ cm/sup -2/ fixed charges at the HfO/sub 2//SiO/sub 2/ interface. We also discuss the role of remote phonon scattering in such gate stacks. Interactions with surface soft-optical phonon of HfO/sub 2/ are clearly evidenced for a metal gate but remain of second order. All these remote interactions are significant for an interfacial oxide thickness up to 2 nm, over which, these are negligible. Finally, the metal gate (TiN) itself induces a modified surface-roughness term that impacts the low to high effective field mobility even for the SiO/sub 2/ gate dielectric references.

Carrier transport in HfO/sub 2//metal gate MOSFETs: physical insight into critical parameters

An advanced CMOS process has been proposed which include key features: 75 nm gate length damascene metal gate, high-k dielectrics with 1.35 nm EOT. Detailed characterisation (TEM, C-V, split C-V, charge pumping, LF noise, low and high temperature transport) demonstrate the high quality of the dielectric and interface. Low Ioff and low gate current make the technology attractive for low standby power applications.

75 nm damascene metal gate and high-k integration for advanced CMOS devices

An advanced CMOS process has been proposed which include key features : 75 nm gate length, damascene metal gate, high-k dielectrics with 1.35 nm equivalent oxide thickness (EOT). Detailed characterisation (TEM, C-V, split C-V, charge pumping, LF noise, low and high temperature transport) demonstrate the high quality of the dielectric and interface Low gate current and low subthreshold slope make it attractive for low stand by power application.

http://ieeexplore.ieee.org/iel5/8537/26991/01200913.pdf

Metal gate and high-k integration for advanced CMOS devices

Experimental results for low and high temperature operation are presented for advanced bulk-Si and fully-depleted SOI (FDSOI) MOSFETs with mid-gap metal gate and high-k gate dielectric. The results are rather similar to those previously obtained in more classical SOI devices in terms of threshold voltage, swing, transconductance or mobility. Moreover, the effective mobility of HfO 2 n- and p-MOSFETs fabricated on bulk Si has been investigated using low-temperature measurements and constant-voltage stress. It was found that Coulomb scattering mechanism has a significant influence on mobility degradation. A correlation between trapped charge and mobility degradation has been made, which can explain the difference observed in mobility behavior in HfO 2 nMOS and pMOS as compared to SiO 2 devices.

Low-temperature performance of ultimate si-based mOSFETs

Advanced channel N and P MOSFETs with HfO 2 gate dielectric and metal gate have been fabricated and exhibit high performance. The effective mobility has been characterized at various temperatures for NMOS and PMOS devices. The electron mobility is lower than in SiO 2 , whereas the hole mobility is relatively unaffected at room temperature but also degraded at low temperatures. The mobility degradation after constant voltage stress suggests a more important Coulomb scattering contribution to mobility as compared to SiO 2 .

Carrier mobility in advanced CMOS devices with metal gate and HfO2 gate dielectric

Handle everyday research tasks with reliable, citation-backed results

Your personal Research Agent to handle research tasks with citation-backed results

Popular Tasks used by Researchers

How can I help with your research?

Meet SciSpace

Get more enhanced response by uploading the PDFs you want me to reference.

No relevant PDFs in your library

SciSpace is the AI research assistant for academics. Run systematic literature reviews on 280M+ papers, and write papers with cited sources. Trusted by 1M+ students, PhDs & researchers.

SciSpace | AI for Research

Analyze PDFs

Code & Manuscripts

Funding & Grants

Literature & Patents

Medical & Clinical Data

Systematic Review

Visualize & Present

Web & Data

Build a Google Scholar-like website for your research.

Build a website

Create charts and images for your research

Create a Chart

Write a paper for submission to a journal

Draft a manuscript

Patent Search

Design eye-catching scientific posters in minutes.

Scientific Poster Generation

Systematic Literature Review

One task is running at the moment. Your messages will be shown right after.

Drag and drop or click here to browse

Loved by <highlight>1 million+</highlight> researchers

Extract a list of specific topics and their sources from unstructured text

Topics

Compare and analyze relevant papers that matches with your search

Papers

Get insights from PDFs and bookmarked papers from your library

My library

Recent searches

Try searching for:

Catch AI-generated content in scholarly and non-scholarly content

{ai} Detector

Ai Writer

Get PDF Summaries, highlighted text explanations 

Chat with PDF

Effortlessly create in-text citations and bibliographies in APA and 2,500 other formats

Citation generator

Get explanations, summaries, and answers on academic papers

Ease up your research workflow with {scispace}'s cohort of exciting AI tools

Elevate your academic writing skills and convey your ideas the way you want

Paraphraser

Explore our range of reading and writing tools

Your file is being prepared and should be ready in a few minutes. If it's a large file, it might take a bit longer. You can close this window, and we'll email you the file when it's done.

You have reached a maximum limit of <strong>{limit}</strong> columns in the table. Remove at least <strong>1</strong> column to add or create another one.

K. Oshima

Author Tools

Chat about Author

Papers

75 nm damascene metal gate and high-k integration for advanced CMOS devices

Metal gate and high-k integration for advanced CMOS devices

Low-temperature performance of ultimate si-based mOSFETs

Carrier mobility in advanced CMOS devices with metal gate and HfO2 gate dielectric