Detecting anomalous events in videos is one of the most popular computer vision topics. It is considered a challenging task in video analysis due to its definition, which is subjective or context-dependent. Various approaches have been proposed to address the anomaly detection problems. These approaches vary from hand-crafted to deep learning. Many researchers have gone into determining the best approach for effectively detecting anomalies in video streams while maintaining a low false alarm rate. The results proved that approaches based on deep learning offer very interesting results in this field. In this paper, we review a family of video anomaly detection approaches based on deep learning techniques, which are compared in terms of their algorithms and models. Moreover, we have grouped state-of-the-art methods into different categories based on the approach adopted to differentiate between normal and abnormal events, and the underlying assumptions. Furthermore, we also present publicly available datasets and evaluation metrics used in existing works. Finally, we provide a comparison and discussion on the results of various approaches according to different datasets. This paper can be a good starting point for such researchers to understand this field and review existing work related to this topic.

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Deep learning-based methods for anomaly detection in video surveillance: a review

Testing of circuits became difficult as the scale of integration is increasing as said in Moore’s Law. Conventional testing approach is not sufficient with the growth of device counts and density. Testing helps the developer to investigate faults and error present in developed circuit which helps to reduce time require to test and thus decreases chances of getting failed during operation. Test time is one of the most important parameters in digital circuit testing which effects the overall process of testing. Reducing the test time of the test pattern generation is one of the most effected solution for the process. Reseeding LFSR is one of the methods to generate the test patterns for testing. In this paper, pseudo-random test patterns are generated to test circuit using reseeding LFSR technique. This helps to reduce the test pattern required to be stored for testing. This technique can be applied with the principles which are required for low power as well as low test data volume. Fault coverage of proposed circuit is calculated using ISCAS’89 benchmark circuits. The technique is integrated with the benchmark circuits and comparison is done based on the performance and resource utilization. Proposed model reduces the need for memory to store seed value and the power utilization. Reseeding can mainly be applied for BIST which targets complete fault coverage and minimization of the test length. Data compression for reducing the test pattern required for testing will indirectly reduce the time required to check the circuits. Future work is to reduce time required for the test pattern generation. Hamming distance can be applied to calculate the number of bits changing during the test patterns transition. Hamming distance approach can be implemented to reduce the parameter.

Reseeding LFSR for Test Pattern Generation

According to Moore’s law, the number of transistors in a chip doubles every eighteen months. Since, the number of transistors is increasing, the probability of finding a fault in the transistors also increases. In order to detect the faults and to avoid potential faults, testing is necessary. In this paper, a power efficient Built-In-Self-Test (BIST) is designed using bit-swapping LFSR and a modified MISR for testing a combinational circuit. The Bit-swapping LFSR is used as the Test Pattern Generator (TPG) and the modified MISR is used as the Output Response Analyzer (ORA). The TPG produces the test patterns, which is given as inputs to the Circuit Under Test (CUT). The ORA analyzes the outputs of the CUT and a pass/fail signal is generated which indicates whether there are any faults in the circuit. This BIST architecture can detect single stuck-at faults present in a combinational circuit. The results were simulated in Xilinx ISE Design Suite 14.4 using VHDL and synthesized in Vivado 2018.2.

Design and Implementation of a Power Efficient BIST

A new type of authentication of a device or chip called Physically Unclonable functions (PUFs) is developed such that, with the built-in manufacturing differences, it provides security. A delay based Physical Unclonable Function (PUF) is implemented in this project on FPGA and its presentation is experimented. By using combinatorial logic, the PUF logic execution is done. In this project, four types of delay PUFs, viz, Arbiter PUF, Xor — Arbiter PUF, Lightweight Secure PUF and Feed Forward PUF are implemented. Delay based PUF utilize built-in delay characteristics of the physical components that alters between chip to chip. Low-cost validation of IC's based on PUFs usage is described. The CRP's usage are for the authentication of a chip or a gadget. The entire project is implemented using Verilog HDL and synthesised with a Xilinx Vivado 2012.2. This project focuses on reducing area consumption, increasing speed and consuming low power.

FPGA based delay PUF implementation for security applications

A Linear Feedback Shift Register (LFSR) is used to generate Pseudo random sequences of bits which can be used in testing a logical circuit. In this work a Test Pattern Generator is implemented which can work as internal LFSR and external LFSR based on the control signal. This module is implemented for different Primitive polynomials from 3bits to 11 bits in Vivado using Zynq-7000 and parameters like utilization, power, and timing are analyzed. The main objective of this work is to increase the length of the Pseudorandom sequences generated by a Test Pattern generator by combining internal and external LFSR using a control signal in a single module. So that, the long test patterns can be generated by using lower bit LFSR.

Design and Analysis of Test Pattern Generator by combining internal and external LFSR

This paper focus on the design of a reconfigurable Linear Feedback Shift Register (LFSR) for Very Large Scale Integration (VLSI) Integrated Circuit (IC) testing. The advancement in VLSI technology have made chip testing more complicated which has lead to the popularity of Logic Built In Self Test (LBIST) compared to Automatic Test Equipment (ATE). Logic BIST allows in-built chip testing with the help of an additional hardware structure inside the circuit. The test patterns are not applied by ATE but are generated by inbuilt testing circuits. Thus it reduces testing costs considerably. LFSR is commonly used as a test pattern generator since it is more efficient than binary counters. Reconfigurable LFSR can be used as the test pattern generator inside Logic BIST to improve the fault coverage of IC testing. As per requirement it can be configured to generate maximum length sequence or any length patterns depending on the feedback polynomial provided. It increases the random patterns generated that are applied as test vectors. The proposed LFSR architecture is simulated in Modelsim RTL simulator. The different sized (16, 32, 64) programmable LFSR structures is synthesized in Xilinx Spartan 3E for implementing LFSR on FPGA. Four structural representations such as Modular, Standard, Hybrid and Complete LFSR are implemented. All the designs are synthesized for ASIC in RTL compiler using 90nm standard cell technology library. The results of the proposed programmable designs are analyzed for speed, power and area.

Design of reconfigurable LFSR for VLSI IC testing in ASIC and FPGA

This paper focus on the design of Programmable MISR(Multiple Input Signature Register) modules for Logic BIST based Very Large Scale Integration(VLSI) Integrated Circuit(IC) testing. The advancement in VLSI technology have made chip testing more complicated which has lead to the popularity of Logic Built In Self Test(LBIST) compared to Automatic Test Equipment(ATE). Logic BIST allows in-built chip testing with the help of an additional hardware structure inside the circuit. The test patterns are not applied by ATE but are generated by inbuilt testing circuits. MISR is commonly used as an output response analyzer since it is alternative to n-parallel LFSRs. MISRs accelerates the testing methodology by compacting multi-bit streams into single signature. A Reconfigurable LFSR can be used as the test pattern generator as well as a response compactor inside Logic BIST to improve the fault coverage of IC testing. The proposed MISR architecture is simulated in Modelsim RTL simulator. The different sized (16, 32, 64) programmable MISR structures is synthesized in Xilinx Spartan 6 for implementing MISR on FPGA. Four structural representations such as Modular, Standard, Hybrid and Complete MISR are implemented. All the designs are synthesized for ASIC in RTL compiler using 90nm standard cell technology library. The results of the proposed programmable designs are analyzed for speed, power and area.

Programmable MISR modules for logic BIST based VLSI testing

This paper focus on the design of Programmable Logic BIST structures for Very Large Scale Integration (VLSI) Integrated Circuit(IC) testing. The advancements happening in VLSI technology day by day have made chip testing more complicated. This has paved way for the increased popularity of Logic Built In Self Test (LBIST) compared to Automatic Test Equipment (ATE). Logic BIST allows self testing of chips with the help of an additional built-in hardware structure inside the circuit. Test-per-scan Logic BIST structure includes Test pattern generator, Response Analyzer, ROM, and Comparator. LFSR does the role of test pattern generator in Logic BIST since it is more efficient than binary counters. MISR is commonly used as an output response analyzer which acts as an alternative to n-parallel LFSRs. Comparator compares the responses stored in ROM and MISR output. Reconfigurability is added to every structural element in BIST to improve the fault coverage of IC testing. The proposed structural architecture is simulated in Modelsim RTL simulator. The different sized (16, 32, 48) programmable structures in Logic BIST were synthesized in Xilinx Spartan 3E and Spartan 6 for implementing them on FPGA. Four structural representations such as Modular, Standard, Hybrid and Complete form were implemented for PRPG and MISR design. All the designs were synthesized in ASIC in RTL compiler using 90nm standard cell technology library. The results of the proposed programmable PRPG and MISR designs were analyzed for speed, power and area with the equivalent modules generated by third party sign-off tool.

Design of efficient programmable test-per-scan logic BIST modules

Physical Unclonable Functions (PUF) are physical entities that generates output as a function of process variation for a given input. It is an emerging hardware security solution to safeguard Intellectual Property, authentication of devices and to ensure data integrity through fingerprint generation. Delay based PUFs forms one of the popular category among different kinds of PUFs wherein the interconnect and gates delays due to uncontrollable manufacturing deviations are exploited to generate secret keys. However some of the designs such as arbiter and butterfly PUFs are seldom implemented in FPGA due to higher component of routing delay in comparison to random delay. This research work focus on the design of Hybrid PUF using the concepts of Butterfly and Arbiter PUF to reduce the skew delay factor in these PUFs. The proposed structure combines the benefits of both PUFs to increase the randomness and accuracy of the arbiter PUF. The architecture is designed to be programmable to work for any N-bit challenge as input. The PUF structures was simulated using Modelsim and Xilinx Vivado software version 19.2 were the tool used for implementing the design in spartan-7 FPGA.

FPGA implementation of programmable Hybrid PUF using Butterfly and Arbiter PUF concepts

As communication technology and e-commerce have improved, credit cards have become the most common mode of payment for both online and offline purchases. As a result, security in this system is expected to be very good to avoid fraudulent transactions. Each year, the number of fraudulent credit card data transfers rises. Researchers are also experimenting with unique approaches to detect and prevent such frauds in this direction. However, some strategies that can accurately and efficiently detect these scams are always needed. This study proposes a method for detecting credit card fraud using supervised and unsupervised learning approaches. The suggested neural network method outperforms existing methods such as Logistic Regression, Local Outlier Factor, Isolation Forest, and K-means clustering when compared. As the accuracy values of each model are nearly negligible because the dataset is imbalanced, we will compare the false-negative rate, recall, precision, and recall parameters of each model.

A Comparative Study on Different Fraud Detection Methods in Credit Card-Based Transactions

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