The radix-2 decimation-in-time fast Hartley transform algorithm for computing the Discrete Hartley Transform (DHT) was introduced by Bracewell. A radix-2 decimation-in-frequency algorithm by Meckelburg and Lipka followed. Prado came up with an in-place version of Bracewells decimation-in-time fast Hartley transform algorithm. A set of fast algorithms for both decimation-in-time and decimation-in-frequency was further developed by Sorenson et al. A new fast radix-2 decimation-in-frequency algorithm for computing the DHT that requires less number of multiplications than those presented by Bracewell, Meckelburg and Lipka, Prado and Sorenson et al is proposed. It exploits the characteristics of the DHT matrix, exhibits stage structures with butterflies similar for each stage and introduces multiplying structures in the signal flow diagram. The operation count for the proposed algorithm is determined. It is verified by implementing the program in C.

A New Fast Radix-2 Decimation-in-Frequency Algorithm for Computing the Discrete Hartley Transform

This study presents a methodology for compressing power system (PS) signals based on the Discrete Hartley Transform (DHT) and develops a computationally efficient approach for calculating power quality (PQ) parameters. Several algorithms are proposed for dynamic bit allocation for coefficient quantization of the DHT. The proposed algorithm was trialed on a real-world signal database and produced better results than those obtained using wavelet transforms. Several scenarios are investigated, and the comparative results are shown.

Hartley Transform Signal Compression and Fast Power Quality Measurements for Smart Grid Application

The elements of the discrete Hartley transform matrix can be computed using the direct method in which each element of the matrix is calculated based on its definition. A position-based method is proposed to simplify the computation. In this method, the characteristics of the discrete Hartley transform matrix are identified and made use of to directly assign values to some elements and compute only a few typical distinct magnitude elements using its definition. These elements are then utilized to obtain the remaining elements based on their positions. An algorithm utilizing this position-based method is developed which is faster in computing the elements than the direct method based on definition.

http://ieeexplore.ieee.org/iel5/4753725/4766377/04766844.pdf

Position-based method for computing the elements of the discrete Hartley transform matrix

The new Proposed design has been designed and developed by novel parallel-pipelined Fast Fourier Transform (FFT) architecture. The most important and fastest efficient algorithm is a FFT. FFT is used to computes the Discrete Fourier Transform (DFT). FFT is mainly applied in autocorrelation, spectrum analysis, linear filtering and pattern recognition system. The proposed architectures were designed by using register minimization and folding transformation technique. The critical path is reduced by pipelining and the multiple inputs and multiple outputs are computed by parallel processing. Furthermore, radix-2, radix- 3, radix-6 Z decimation in time and decimation in frequency algorithm can be used. As a result, the radix-6 Z has been developed to reduce the complexity of hardware and the computational intension. The power dissipation can be decreased and unwanted operations are stopped by using the clock gates.

Parallel-Pipelined Radix-6 Z Multipath Delay Commutator FFT Architectures

Fast Fourier Transform (FFT) is a most proficient algorithm for computing the Discrete Fourier Transform (DFT). FFT is specially used in analysis of autocorrelation, disambiguation, recognition of patterns, statistics and data analysis. The new proposed algorithm for computing a length L=2 B x3 C FFT. It is used to minimize the twist of hardware depict and arithmetic operations. Additionally, the propound fragment design can accomplish by the mixer of radix-3 and radix-2 B x3 C FFT algorithm. It is entirely changeable of Split Radix Fast Fourier Transform (SRFFT) algorithm. As a consequence, the new proffer design of length L is used to belittle the area of system on chips and mathematical calculation. More compromise can achieve by combining the two architectures implemented in the same FFT. It naturally furnishes a broad selection of accessible length of FFT’s.

Area minimized fft architecture using split radix algorithm for length l=radix-3 and radix-2bx3c

Fast algorithms of a transform, like fast Fourier transform (FFT) algorithms, are based on different decomposition techniques. It is shown that these decomposition techniques can also be applied to the computation of the discrete Hartley transform (DHT) for a real-valued sequence. Recently, an efficient decomposition technique for radix-3 decimation-in-time (DIT) FFT and fast Hartley transform (FHT) algorithms has been demonstrated. Such a decomposition technique is implemented for radix-3 and -6 decimation-in-frequency (DIF) FHT algorithms and found to improve the operation count. Efficiency in these algorithms is derived by pairing the rotating factors with an appropriate reordering of the input sequence. From the results, it is seen that the radix-3 and -6 FHT algorithms presented are comparable to the split-radix FHT algorithm in terms of their operation count and will be more efficient when the sequence length is closer to an integer power of the corresponding radix.

New radix-3 and −6 decimation-in-frequency fast Hartley transform algorithms

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New radix-3 and −6 decimation-in-frequency fast Hartley transform algorithms