The Roofline model offers insight on how to improve the performance of software and hardware.

/pdf/roofline-an-insightful-visual-performance-model-for-1t7yjuvfwn.pdf

Roofline: an insightful visual performance model for multicore architectures

Writing programs that scale with increasing numbers of cores should be as easy as writing programs for sequential computers

https://dl.acm.org/doi/pdf/10.1145/1562764.1562783

A view of the parallel computing landscape

Scientific discovery and engineering innovation requires unifying traditionally separated high-performance computing and big data analytics.

Exascale computing and big data

General-Purpose Graphics Processing Units (GPGPUs) are promising parallel platforms for high performance computing. The CUDA (Compute Unified Device Architecture) programming model provides improved programmability for general computing on GPGPUs. However, its unique execution model and memory model still pose significant challenges for developers of efficient GPGPU code. This paper proposes a new programming interface, called OpenMPC, which builds on OpenMP to provide an abstraction of the complex CUDA programming model and offers high-level controls of the involved parameters and optimizations. We have developed a fully automatic compilation and user-assisted tuning system supporting OpenMPC. In addition to a range of compiler transformations and optimizations, the system includes tuning capabilities for generating, pruning, and navigating the search space of compilation variants. Our results demonstrate that OpenMPC offers both programmability and tunability. Our system achieves 88% of the performance of the hand-coded CUDA programs.

/pdf/openmpc-extended-openmp-programming-and-tuning-for-gpus-2eiphdxbfr.pdf

OpenMPC: Extended OpenMP Programming and Tuning for GPUs

Although stencil auto-tuning has shown tremendous potential in effectively utilizing architectural resources, it has hitherto been limited to single kernel instantiations; in addition, the large variety of stencil kernels used in practice makes this computation pattern difficult to assemble into a library This work presents a stencil auto-tuning framework that significantly advances programmer productivity by automatically converting a straightforward sequential Fortran 95 stencil expression into tuned parallel implementations in Fortran, C, or CUDA, thus allowing performance portability across diverse computer architectures, including the AMD Barcelona, Intel Nehalem, Sun Victoria Falls, and the latest NVIDIA GPUs Results show that our generalized methodology delivers significant performance gains of up to 22× speedup over the reference serial implementation Overall we demonstrate that such domain-specific auto-tuners hold enormous promise for architectural efficiency, programmer productivity, performance portability, and algorithmic adaptability on existing and emerging multicore systems

/pdf/an-auto-tuning-framework-for-parallel-multicore-stencil-41vieuyhow.pdf

An auto-tuning framework for parallel multicore stencil computations

Stencil Computation Optimization and Auto-tuning on State-of-the-Art Multicore Architectures Kaushik Datta ∗† , Mark Murphy † , Vasily Volkov † , Samuel Williams ∗† , Jonathan Carter ∗ , Leonid Oliker ∗† , David Patterson ∗† , John Shalf ∗ , and Katherine Yelick ∗† CRD/NERSC, Lawrence Berkeley National Laboratory, Berkeley, CA 94720, USA Computer Science Division, University of California at Berkeley, Berkeley, CA 94720, USA Abstract Understanding the most efﬁcient design and utilization of emerging multicore systems is one of the most chal- lenging questions faced by the mainstream and scientiﬁc computing industries in several decades Our work ex- plores multicore stencil (nearest-neighbor) computations — a class of algorithms at the heart of many structured grid codes, including PDE solvers We develop a number of effective optimization strategies, and build an auto-tuning environment that searches over our optimizations and their parameters to minimize runtime, while maximizing performance portability To evaluate the effectiveness of these strategies we explore the broadest set of multicore architectures in the current HPC literature, including the Intel Clovertown, AMD Barcelona, Sun Victoria Falls, IBM QS22 PowerXCell 8i, and NVIDIA GTX280 Overall, our auto-tuning optimization methodology results in the fastest multicore stencil performance to date Finally, we present several key insights into the architectural trade- offs of emerging multicore designs and their implications on scientiﬁc algorithm development 1 Introduction The computing industry has recently moved away from exponential scaling of clock frequency toward chip mul- tiprocessors (CMPs) in order to better manage trade-offs among performance, energy efﬁciency, and reliability [1] Because this design approach is relatively immature, there is a vast diversity of available CMP architectures System designers and programmers are confronted with a confus- ing variety of architectural features, such as multicore, SIMD, simultaneous multithreading, core heterogeneity, and unconventional memory hierarchies, often combined in novel arrangements Given the current ﬂux in CMP design, it is unclear which architectural philosophy is best suited for a given class of algorithms Likewise, this architectural diversity leads to uncertainty on how to refactor existing algorithms and tune them to take the maximum advantage of existing and emerging platforms Understanding the most efﬁcient design and utilization of these increasingly parallel multicore systems is one of the most challenging questions faced by the computing industry since it began This work presents a comprehensive set of multicore optimizations for stencil (nearest-neigbor) computations — a class of algorithms at the heart of most calculations involving structured (rectangular) grids, including both implicit and explicit partial differential equation (PDE) solvers Our work explores the relatively simple 3D heat equation, which can be used as a proxy for more complex stencil calculations In addition to their importance in scientiﬁc calculations, stencils are interesting as an archi- tectural evaluation benchmark because they have abundant parallelism and low computational intensity, offering a mixture of opportunities for on-chip parallelism and chal- lenges for associated memory systems Our optimizations include NUMA afﬁnity, array padding, core/register blocking, prefetching, and SIMDiza- tion — as well as novel stencil algorithmic transformations that leverage multicore resources: thread blocking and circular queues Since there are complex and unpredictable interactions between our optimizations and the underlying architectures, we develop an auto-tuning environment for stencil codes that searches over a set of optimizations and their parameters to minimize runtime and provide performance portability across the breadth of existing and future architectures We believe such application-speciﬁc auto-tuners are the most practical near-term approach for obtaining high performance on multicore systems To evaluate the effectiveness of our optimization strate- gies we explore the broadest set of multicore archi- tectures in the current HPC literature, including the out-of-order cache-based microprocessor designs of the dual-socket×quad-core AMD Barcelona and the dual- socket×quad-core Intel Clovertown, the heterogeneous local-store based architecture of the dual-socket×eight- core fast double precision STI Cell QS22 PowerX- Cell 8i Blade, as well as one of the ﬁrst scientiﬁc studies of the hardware-multithreaded dual-socket×eight- core×eight-thread Sun Victoria Falls machine Addition- ally, we present results on the single-socket×240-core mul- tithreaded streaming NVIDIA GeForce GTX280 general purpose graphics processing unit (GPGPU) This suite of architectures allows us to compare the mainstream multicore approach of replicating conventional cores that emphasize serial performance (Barcelona and

/pdf/stencil-computation-optimization-and-auto-tuning-on-state-of-30h2ljvncn.pdf

Stencil computation optimization and auto-tuning on state-of-the-art multicore architectures. - eScholarship

Code Generators •Kernel-specific •Perl script generates 1000’s of code variations •Autotuner searches over all possible implementations (sometimes guided by a performance model to prune the space) to find the optimal configuration •Optimizations included in this work: • NUMA-Aware collocates data with the threads processing it • Array Padding avoids conflicts in the L1/L2 • Thread/Cache minimizes cache misses and memory traffic Blocking • Vectorization avoids rolling the TLB • Unrolling/DLP compensates for poor compilers • SW Prefetching attempts to hide L2 and DRAM latency • SIMDization compensates for poor compilers, and streaming stores minimize memory traffic Autotuning Lattice Methods

/pdf/autotuning-structured-grid-kernels-1e975gc5hi.pdf

Autotuning Structured Grid Kernels

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Stencil computation optimization and auto-tuning on state-of-the-art multicore architectures. - eScholarship

Autotuning Structured Grid Kernels