A germanosilicide technology employing Ni0.95Pd0.05 alloy to improve the germanosilicide film texture strucutre on relaxed Si1−xGex substrate has been developed. Highly oriented (Ni0.95Pd0.05)y(Si1−xGex)1−y films where x=0.2, 0.25, 0.3, and y≈0.5 are obtained at 400 °C annealing with (200) as the preferred orientation, as was revealed by cross-sectional transmission electron microscopy and x-ray diffraction results. The formation of the highly oriented (Ni0.95Pd0.05)y(Si1−xGex)1−y film can be explained by interface and surface energies minimization due to the addition of Pd.

Highly oriented Ni(Pd)SiGe formation at 400 °C

Void free epitaxial-CoSi 2 with nano-thickness has been successfully fabricated on narrow Si(100) substrates surrounded by shallow trench isolation (STI) using a capped titanium mediated epitaxy method The silicide is epitaxial with a CoSi 2 (110)∥Si(100) crystal orientation Void growth in the narrow silicon lines under the film edges due to an anomalous creep effect in the presence of a localized tensile stress between CoSi 2 and Si was suppressed completely by optimizing the initial rapid thermal annealing (RTA) thermal budget, and ensuring that no voids nucleated prior to the selective wet clean and second higher-temperature RTA process The epitaxial Co-silicided n/p metal oxide semiconductor field effect transistors show excellent device performance

http://esl.ecsdl.org/content/7/11/H49.full.pdf

Uniform void-free epitaxial CoSi2 formation on STI bounded narrow Si(100) lines by template layer stress reduction

We report experimental findings on the thermal-induced stress-voiding observed during epitaxial CoSi2 formation on patterned Si(100) wafers associated with the Co/Ti-interposing layer scheme [1-6]. The first rapid thermal process (RTP) in a typical SALICIDE process was studied by varying the temperature and the RTP ramp-up rate. Based on ex-situ cross-sectional transmission electron microscopy (XTEM), crystal defects were observed at shallow trench isolation (STI)/Si and gate spacer/Si edges after annealing at temperatures greater than 520°C. In addition, isothermal anneals for various time periods resulted in increased encroachment of an ultra-thin CoSi2-phase at the STI/Si edge. Higher temperature anneals also resulted in a corresponding increase in void size. In addition, higher ramp-up rates led to a thicker CoSi2 “pocket” film at the tensile-stressed STI/Si edge, aligned epitaxially along the {111}-habit planes. Our attempts to bypass the CoSi formation in order to alleviate the anomalous Si diffusion was found to be irrelevant to the voiding issue, due to the inherent nature of this film stack system to nucleate CoSi2 as the first phase. By comparing our experimental observations of voiding with Hu’s analysis of the trench isolation stress fields, we found good agreement with the predicted stress field distribution in the active Si and STI/Si edge with the locations of void nucleation. The anomalously large stress induced is still not known, but can be attributed to the encroaching CoSi2 film which tends to realign epitaxially along the STI/Si interface.

Thermal Studies on Stress-Induced Void-Like Defects in Epitaxial-CoSi2 Formation

NMOS and PMOS transistors of various (W/L) ratios, down to 0.24µm channel length, have been used to investigate the effects of copper diffusion (from the backside) on their electrical parameters. A thin layer of copper film was deposited on the back surface of the wafer. Over 10 hours of annealing at 4000C was carried out. Electrical parameters such as the threshold voltage (VT0), the drain saturation current (IDsat) and the off-current (Ioff), for transistors, and the leakage current for large diodes were measured. Secondary Ion Mass Spectroscopy (SIMS) was used to monitor the copper diffusion. Even after 10 hours of annealing at 400°C, electrical parameters of both NMOS and PMOS devices and leakage currents of diodes showed no significant degradation.

https://www.cambridge.org/core/services/aop-cambridge-core/content/view/S194642740059811X

Backside Copper Contamination Issues in CMOS Process Integration–A Case Study

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Thermal Studies on Stress-Induced Void-Like Defects in Epitaxial-CoSi2 Formation

Backside Copper Contamination Issues in CMOS Process Integration–A Case Study