44 Papers
67 Citations
Junichi Hattori is an academic researcher from National Institute of Advanced Industrial Science and Technology. The author has contributed to research in topics: Field-effect transistor & Capacitance. The author has an hindex of 8, co-authored 32 publications.
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Papers
Fully coupled 3-D device simulation of negative capacitance FinFETs for sub 10 nm integration
Hiroyuki Ota,Tsutomu Ikegami,Junichi Hattori,Koichi Fukuda,Shinji Migita,Akira Toriumi +5 more
- 01 Dec 2016
TL;DR: In this paper, the performance of negative capacitance FinFETs at sub 10 nm gate length is analyzed with a newly developed technology computer-aided design (TCAD) simulation.
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Material and device engineering in fully depleted silicon-on-insulator transistors to realize a steep subthreshold swing using negative capacitance
TL;DR: In this article, a negative dielectric constant (NDC) was proposed for field effect transistors (FETs) with HfO2-based gate insulators to attain a precipitous sub-threshold swing (SS) by exploiting negative capacitance.
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A TCAD device simulator for exotic materials and its application to a negative-capacitance FET
TL;DR: The Impulse TCAD simulator as mentioned in this paper is built on top of a nonlinear finite volume method solver, which is further based on the Python script language and its associated scientific libraries, allowing the user to fully customize the device properties and/or equations using scripts, which allows ready handling of exotic materials with nonstandard physical models.
25
Demonstrating performance improvement of complementary TFET circuits by I on enhancement based on isoelectronic trap technology
Takahiro Mori,Hidehiro Asai,Junichi Hattori,K. Fukuda,Shintaro Otsuka,Yukinori Morita,Shin-ichi O'uchi,Hiroshi Fuketa,Shinji Migita,Wataru Mizubayashi,Hiroyuki Ota,Takashi Matsukawa +11 more
- 01 Dec 2016
TL;DR: In this paper, the performance of a complementary circuit comprising Si-based tunnel field effect transistors (TFETs) was improved by using isoelectronic trap (IET) technology.
14
Structural advantages of silicon-on-insulator FETs over FinFETs in steep subthreshold-swing operation in ferroelectric-gate FETs
TL;DR: In this paper, the subthreshold operation of fully depleted silicon-on-insulator FETs and FinFETs, with embedded ferroelectric negative-capacitance gate insulators, using technology computer-aided design simulations, is discussed.
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