http://ieeexplore.ieee.org/iel5/5610941/5624686/05624745.pdf

Power electronics

This paper proposes a low-power complementary metal–oxide–semiconductor (CMOS) smart temperature sensor in order to obtain self-refresh control for low-power memory cells. The multiple-block system is composed of a temperature-to-pulse generator (TPG), a time-to-digital converter (TDC), and a frequency selector. A pulse-shrinking system with an inverter-based delay line is used for feedback topology in the TDC. A temperature-independent current reference is applied for temperature compensation in the ring-oscillator and delay line in the TPG. The small-size time-mode temperature sensor is designed using a 0.35- $\mu \text{m}$ CMOS process. Six different digital outputs are obtained for temperature ranging between −40 °C and 100 °C. Measurement shows that the proposed temperature sensor operates with a power dissipation of $0.075~\mu \text{W}$ per sample and a die area of 0.08 mm2. The output frequency is shown to increase exponentially with variations in temperature, while the shrinking pulse in the TDC shows linear dependence on temperature.

CMOS Integrated Time-Mode Temperature Sensor for Self-Refresh Control in DRAM Memory Cell

In this paper, a novel quadrature voltage-controlled oscillator (QVCO) coupled by four capacitors is presented. Comparing with the conventional transformer and MOS transistor coupling, the proposed QVCO achieves better phase noise and lower power dissipation. The proposed QVCO is verified with GlobalFoundries’ 0.18 μm CMOS 1P6M RF process using Cadence IC Design Tools. The simulation results demonstrate that the proposed QVCO operates from 2.05 to 5.25 GHz by adjusting the bias voltage, and its phase noise is −143.6 dBc/Hz at 1 MHz offset. Moreover, the power consumption of the QVCO is only 2.8 mW with 1.3 V supply voltage.

Novel Quadrature Voltage-Controlled Oscillator Using Capacitor Coupling

Low power quadrature voltage controlled oscillator

Nonalcoholic fatty liver disease (NAFLD) has become the most common chronic liver disease worldwide, whereas there is no approved drug therapy for it due to its complexity. Studies are emerging to discuss the role of selective autophagy in the pathogenesis of NAFLD, because the specificity among the features of selective autophagy makes it a crucial process in mitigating hepatocyte damage caused by aberrant accumulation of dysfunctional organelles, for which no other pathway can compensate. of Review This review aims to summarize the types, functions, and dynamics of selective autophagy that are of particular importance in the initiation and progression of NAFLD. And on this basis, the review outlined the therapeutic strategies against NAFLD, in particular the medications and potential natural products that can modulate selective autophagy in the pathogenesis of this disease. Key Scientific Concepts of Review The critical roles of lipophagy and mitophagy in the pathogenesis of NAFLD are well established, while reticulophagy and pexophagy are still being identified in this disease due to the insufficient understanding of their molecular details. As gradual blockage of autophagic flux reveals the complexity of NAFLD, studies unraveling the underlying mechanisms have made it possible to successfully treat NAFLD with multiple pharmacological compounds that target associated pathways. Overall, it is convinced that the continued research into selective autophagy occurring in NAFLD will further enhance the understanding of the pathogenesis and uncover novel therapeutic targets. 

Mechanisms and therapeutic implications of selective autophagy in nonalcoholic fatty liver disease.

Lipophagy, a type of autophagy that breaks down lipid droplets, is essential in the regulation of intracellular lipid accumulation and intracellular free fatty acid levels in numerous organisms and metabolic conditions. We investigated the effects of Stevia rebaudiana Bertoni (S), a low-calorie sweetener, and stevioside (SS) on hepatic steatosis and autophagy in hepatocytes, as well as in db/db mice. S and SS reduced the body and liver weight and levels of serum triglyceride, total cholesterol, and hepatic lipogenic proteins. In addition, S and SS increased the levels of fatty acid oxidase, peroxisome proliferator-activated receptor alpha (PPARα), and microtubule-associated protein light chain 3 B but decreased that of sequestosome 1 (p62) in the liver of db/db mice. Additionally, Beclin 1, lysosomal associated membrane protein 1, and phosphorylated adenosine monophosphate-activated protein kinase protein expression was augmented following S and SS treatment of db/db mice. Furthermore, the knockdown of PPARα blocked lipophagy in response to SS treatment in HepG2 cells. These outcomes indicate that PPARα-dependent lipophagy is involved in hepatic steatosis in the db/db mouse model and that SS, a PPARα agonist, represents a new therapeutic option for managing associated diseases.

/pdf/stevia-and-stevioside-attenuate-liver-steatosis-through-1dberbv8.pdf

Stevia and Stevioside Attenuate Liver Steatosis through PPARα-Mediated Lipophagy in db/db Mice Hepatocytes

This paper presents a dual-mode CMOS integrated DC-DC buck converter for portable application. The proposed dual-mode buck converter is designed to be controlled by PFM (pulse frequency modulation) and PWM (pulse width modulation) modes. The converter for the application of wide current range and high power efficiency is used to generate the voltage of 0.5–3.0 V with the battery source of 3.3–5.0 V which has the load current range of 30–200 mA. PFM control is applied to obtain high power efficiency when the load-current is low under 50 mA, while PWM is designed to be operated in the higher range of load-current. A ring-type VCO (voltage-controlled oscillator) is used in PFM circuit and provides a variable frequency to correspond to the output current. In PWM control circuit, the combination of sensing current and ramp signal are applied in feedback circuit of converter. The proposed dual-mode DC-DC buck converter is integrated with 0.18 μm CMOS process. Simulation result shows that the converter provides the well-regulated line and load regulations with power efficiency of 80–90%.

High performance CMOS integrated PWM/PFM dual-mode DC-DC buck converter

This paper proposes a high performance frequency divider which is composed of injection-locked frequency divider (ILFD) and current-mode logic (CML) frequency divider. The multiple-block divider is to obtain the broad-band and high frequency operation in phase-locked loop (PLL). ILFD has a similar structure with LC cross-coupled oscillator which operates at 20 GHz. 3 stages of ILFD are supposed to provide the operation of divide-by-8 (/8) with low power consumption and are to adjust the frequency alignment with the LC cross-coupled oscillator. CML frequency divider which is used as the 2nd block of divider applies an inductive peaking structure in order to increase the bandwidth. The proposed frequency divider which has the /8 ILFD and /32 CML frequency divider is integrated with 0.18 µm CMOS process and operates in the conventional PLL. Simulation test shows the low power consumption of 13.2 mW at the input frequency of 20 GHz.

Low Power CMOS 8:1 Injection-Locked Frequency Divider with LC Cross-Coupled Oscillator

In this paper, a high performance frequency divider is introduced in an integrated CMOS phase-locked loop (PLL). An injection-locked frequency divider (ILFD) is designed with a current-mode logic (CML) frequency divider to obtain the broad-band and high frequency operation. LC cross-coupled oscillator operates at 50 GHz and ILFD is supposed to provide the operation of divide-by-2 (/2). ILFD has a similar structure with the oscillator to adjust the frequency alignment between the oscillator and ILFD. As the 2nd-stage divider, CML frequency divider is applied with an inductive peaking structure. The proposed frequency divider is applied in the conventional PLL which is integrated with 0.18 µm CMOS process. Simulation test shows that the /2 ILFD and /128 CML frequency divider is operated at the input frequency of 50 GHz with the power consumption of 30 mW.

High performance injection-locked frequency divider with 50 GHz LC cross-coupled oscillator in 0.18 µm CMOS process

Purpose




This paper aims to propose a low-power complementary MOS (CMOS) current sensor for control circuit in an integrated DC-DC buck converter.




Design/methodology/approach




The integrated DC-DC converter, which is composed of feedback control circuit and power block, is designed with 0.35-µm CMOS process. Current sensor in the control circuit is integrated with sense-FET and voltage-follower circuits to reduce power consumption and improve its sensing accuracy. In the current-sensing circuit, the size ratio of the power metal oxide semiconductor field effect transistor (MOSFET) to the sensing transistor (K) is 1,000, and a current-mirror is used for a voltage follower. N-channel MOS acts as a switching device in the current-sensing circuit, where the sensing FET is in parallel with the power MOSFET. The amplifier and comparator are designed to obtain a high gain and a fast transient time.




Findings




Experiment shows that the current sensor is operated with accuracy of more than 85 per cent, and the transient time of the error amplifier is controlled within 100 µs. The sensing current is in the range of a few hundred µA at a frequency of 0.6-2 MHz and an input voltage of 3-5 V. The output voltage is obtained as expected with the ripple ratio within 5 per cent.




Originality/value




The proposed current sensor in DC-DC converter provides an accurately sensed inductor current with a significant reduction in power consumption in the range of 0.2 mW. High-accuracy regulation is obtained using the proposed current sensor. As the sensor utilizes simple switch-type voltage follower and sense-FET, it can be widely applied to other low-power applications such as high-frequency oscillator and over-current protection circuit.

Low-power CMOS integrated current sensor for current-mode DC-DC buck converter

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