The processing delay is a serious constraint for speech communication. A one-way end-to-end delay of more than 150 ms can severely degrade the quality of real-time conversations. The components of the total system delay includes the speech frame size, the look ahead, other algorithmic delays, multiplexing delay, processing delay for computation, and transmission delay. At the transcoder rate adaptor unit (TRAU), the only delay that can be manipulated is the processing delay. The TRAUs are generally positioned remote to the base transceiver station (BTS). The channel codec units (CCUs) are located in the BTS. In general, 16 kbit/s traffic channels can be used for full rate speech between the TRAU and BTS. By putting the TRAU remote to the BTS, DSPs for speech coding can be utilized more efficiently to cut system cost. High performance DSPs, such as the Lucent DSP16000, can be used to further cut the cost per speech channel. This article presents an implementation of GSM enhanced full rate (EFR) codec on the Lucent Technologies' DSP16000. The original European Telecommunications Standards Institute (ETSI) C code has been restructured to address the issues of MIPS (million instructions per second), RAM usage, and processing delay. We give a performance overview of vocoder implementations on some existing fixed-point DSPs and discuss the architecture of the DSP16000. Details on how the ETSI C code is restructured are presented. The DSP16210 implementation results are then discussed.

High-performance DSPs

This paper presents designs for parallel saturating multioperand adders. These adders have only a single carrypropagate adder on the critical delay path, yet produce the same results that would be obtained if the additions were performed serially with saturation after each operation. When used with parallel saturating multipliers or multiplyaccumulate units, these adders signi cantly improve the performance of GSM speech coders. They can also easily be modi ed to perform either saturating or wraparound multioperand addition, based on an input control signal. Since parallel saturating multioperand adders have more area and less delay than serial saturating multioperand adders, they are suitable for high-performance digital signal processing systems.

Parallel saturating multioperand adders

The Global System for Mobile (GSM) communications uses a 13Kbps vocoder which expands to 228Kbps after channel codiilg To increase the user capacity the half-rate chumlel has a gross transfer rate of 114Kbps The vocoder for the hulf-rate channels operates at 56Kbps To obtain better performance, GSM introduced eilhanced full-rate vocoder which operates at 122Kbps The computational requirements of these vocoders require the design of an entirely new digital signal processing architecture geared towards 1-D signal and speech processing In this paper, at first the architecture of a specific design for full-rate vocoder is introduced, then according to the results of this architecture and common features available in all ttu-ee vocoders, a DSP Core for implementing these vocoders is suggested The architecture of the DSP Core is characterized by pipelining and parallel operation of functional units This Core is a 16-bit fixed-point processor implemented on an FPGA and can be used as a real-time GSM vocoder

Motivation from a Full-Rate Specific Design to a DSP Core Approach for GSM Vocoders

The TETRA (terrestrial trunked radio) speech codec is mandatory for all TETRA mobiles and networks. This paper presents the cost-effective implementation of the TETRA speech codec using the primitive functions of the compiler for the 16 bit fixed-point eDSP (embedded DSP), which was developed by ETRI for the purpose of use in various SoCs. Generally, the simple implementation of the speech codec is using the cross compiling but it probably does not operate in real-time. The more optimized implementation is the fully hand-written assembly code but this approach is very time consuming compared to the cross compiling methods. More efficient way is using the cross compiling with the primitive functions. In this way, we convert the basic arithmetic function in TETRA speech codec into the compact one using primitive functions of the compiler in order to reduce the computation where we used the in-house compiler of the eDSP. Employing the primitive functions makes it possible to obtain the optimized assembly code because our compiler is fully customized to the eDSP. The number of cycles can be reduced into the 8 % of the complexity of the simple cross compiling version. We also describe the comparison among some implementation approaches and their results.

Cost-effective implementation of TETRA codec using the primitive functions of the compiler

The Global System for Mobile (GSM) communications uses a 13Kbps vocoder which expands to 22.8Kbps after channel coding. To increase the user capacity the half-rate channel has a gross transfer rate of 11.4Kbps. The vocoder for the half-rate channels operates at 5.6Kbps. To obtain better performance, GSM introduced enhanced full-rate vocoder which operates at 12.2Kbps. The computational requirements of these vocoders require the design of an entirely new digital signal processing architecture geared towards 1-D signal and speech processing. In this paper, at first the architecture of a specific design for full-rate vocoder is introduced, then according to the results of this architecture and common features available in all three vocoders, a DSP Core for implementing these vocoders is suggested. The architecture of the DSP Core is characterized by pipelining and parallel operation of functional units. This Core is a 16-bit fixed-point processor implemented on an FPGA and can be used as a real-time GSM vocoder.

Motivation from a full-rate specific design to a DSP core approach for GSM vocoders

An implementation of GSM EFR using traditional single MAC DSPs (DSP1600) takes 24 MIPS to run a single speech channel. Lucent DSP16000 is a dual MAC high performance DSP. Analysis has shown DSP16000 code can run GSM EFR at 10 MIPS per channel with the same program space as DSP1600. The code has been re-structured to minimize the delays and RAM usage for multi-channel transcoder/rate adapter units (TRAU) applications. For a 100 MIPS DSP16210 running 6 EFR speech channels, DSP16210 code takes 15.7 K words of RAM with 3.2 ms maximum delay for the encoder and 0.5 ms for the decoder. Without re-structuring, the numbers are 27 K, 15.4 ms and 1.5 ms respectively. This makes the DSP16000 very attractive for TRAU applications. The initial implementation runs at 12.8 MIPS per channel with 19.3 K words of RAM, 4.7 ms maximum encoding delay and 0.5 ms maximum decoding delay for 6 speech channels.

GSM EFR implementation for TRAU application on DSP16000

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GSM EFR implementation for TRAU application on DSP16000