Neuromorphic computing has come to refer to a variety of brain-inspired computers, devices, and models that contrast the pervasive von Neumann computer architecture This biologically inspired approach has created highly connected synthetic neurons and synapses that can be used to model neuroscience theories as well as solve challenging machine learning problems The promise of the technology is to create a brain-like ability to learn and adapt, but the technical challenges are significant, starting with an accurate neuroscience model of how the brain works, to finding materials and engineering breakthroughs to build devices to support these models, to creating a programming framework so the systems can learn, to creating applications with brain-like capabilities In this work, we provide a comprehensive survey of the research and motivations for neuromorphic computing over its history We begin with a 35-year review of the motivations and drivers of neuromorphic computing, then look at the major research areas of the field, which we define as neuro-inspired models, algorithms and learning approaches, hardware and devices, supporting systems, and finally applications We conclude with a broad discussion on the major research topics that need to be addressed in the coming years to see the promise of neuromorphic computing fulfilled The goals of this work are to provide an exhaustive review of the research conducted in neuromorphic computing since the inception of the term, and to motivate further work by illuminating gaps in the field where new research is needed

A Survey of Neuromorphic Computing and Neural Networks in Hardware.

This study presents experimental realizations of the HR neuron model with programmable hardware and synchronization applications. The HR neuron model exhibiting burst, spike, and chaotic dynamics has been implemented with both FPAA (Field Programmable Analog Array) and FPGA (Field Programmable Gate Array) devices. These devices provide flexible design possibilities such as reducing the complexity of design, real-time modification, software control and adjustment within the system. And it is also examined experimentally that how the synchronization of two HR neurons are able to achieve by using these hardware. The experimental results obtained from FPAA and FPGA based realizations agree with the numerical simulations very well.

Experimental realizations of the HR neuron model with programmable hardware and synchronization applications

The low-voltage low-power sinh-domain (SD) implementations of integer- and fractional-order FitzHugh–Nagumo (FHN) neuron model have been introduced in this paper. Besides, the effect of fractional-orders on the external excitation current and dynamics of the neuron has been examined in this paper. The proposed SD designs of FHN neuron model have the benefits of: 1) low-voltage operation; 2) integrability, due to resistor-less design and the employment of only grounded components; 3) electronic tunability of performance parameters; and 4) low-power implementation due to the inherent properties of SD technique. HSPICE simulator tool and Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan 130-nm CMOS process was used to evaluate and verify the correct functioning of the model. In addition, to experimentally verify the operation of the proposed fractional-order FHN neuron model, field-programmable analog array (FPAA) implementation of the model has been presented, and the proper functioning of the model has been verified. To the best of the authors’ knowledge, this is the first paper that describes the electronic realization of the fractional-order FHN neuron model. In addition, it is the first time that the FPAA implementation of any fractional-order neuron model has been presented.

Low-Voltage Low-Power Integrable CMOS Circuit Implementation of Integer- and Fractional–Order FitzHugh–Nagumo Neuron Model

The explosion of &#x201C;big data&#x201D; applications imposes severe challenges of speed and scalability on traditional computer systems. As the performance of traditional Von Neumann machines is greatly hindered by the increasing performance gap between CPU and memory (&#x201C;known as the memory wall&#x201D;), neuromorphic computing systems have gained considerable attention. The biology-plausible computing paradigm carries out computing by emulating the charging/discharging process of neuron and synapse potential. The unique spike domain information encoding enables asynchronous event driven computation and communication, and hence has the potential for very high energy efficiency. This survey reviews computing models and hardware platforms of existing neuromorphic computing systems. Neuron and synapse models are first introduced, followed by the discussion on how they will affect hardware design. Case studies of several representative hardware platforms, including their architecture and software ecosystems, are further presented. Lastly we present several future research directions. 

A Survey on Neuromorphic Computing: Models and Hardware

This contribution introduced and investigated an improved photosensitive memristive FitzHugh–Nagumo (FHN) neural circuit. The mathematical equations of the model have been derived from Kirchhoff’s electrical circuit law. Based on Helmholtz’s theorem, the Hamilton statistical function that enables us to obtain the physical energy of the neuron necessary to sustain electrical activity has been established. Therefore, the energy dependency on the light intensity and the magnetic field has been provided. Using two-parameter diagrams, bifurcation diagrams, Lyapunov exponents, and time series, the window of parameters in which regular and irregular patterns of the neuron occur have been characterized. Besides, the proposed FHN neuron model is implemented using a simple microcontroller platform and various firing patterns are acquired experimentally to validate the numerical results. Furthermore, light and field-induced pattern formation in a chain regular lattice network made of 100 photosensitive memristive neurons is being studied. Numerical experiments are carried out to identify the effects of photocurrent and magnetic flux parameters on information coding patterns translated by the membrane potential from voltage output. The spatiotemporal patterns revealed that the network presents localized wave patterns with some features of synchronization, sensitive to parameter change. This confirms that information coding and other collective behaviors of the network could be efficiently controlled by taming the intensity of light illumination and magnetic field exposure. 

An enhanced FitzHugh–Nagumo neuron circuit, microcontroller-based hardware implementation: Light illumination and magnetic field effects on information patterns

In this paper, a low power and low jitter 12-bit CMOS digitally controlled oscillator (DCO) design is presented. The CMOS DCO is designed based on a ring oscillator implemented with Schmitt trigger based inverters. Simulations of the proposed DCO using 32 nm CMOS predictive transistor model (PTM) achieves controllable frequency range of 570 MHz~850 MHz with a wide linearity. Monte Carlo simulation demonstrates that the time-period jitter due to random power supply fluctuation is under 75 ps and the power consumption is 2.3 mW at 800 MHz with 0.9 V power supply.

A 12-bit digitally controlled oscillator with low power consumption

A simple neuron model, the FitzHugh-Nagumo (FHN) model, is implemented on field programmable analog arrays (FPAAs). The differential equations of the model is integrated by making arithmetic operations on the reconfigurable voltage model circuits of the FPAAs. The simulation and implementation results demonstrate that FPAA is the viable candidate for the neuron hardware implementation in real time or many orders of magnitude faster.

Circuit implementation of FitzHugh-Nagumo neuron model using Field Programmable Analog Arrays

An all-digital phase-locked loop (ADPLL) with fast acquisition and low power digitally controlled oscillator (DCO) is presented. The proposed ADPLL is designed with a unique lock-in process by employing a time-to-digital converter. Both the frequency of the reference clock and the delay between DCO output and DCO clock are measured. A carefully designed reset process reduces the phase lock into two cycles. The ADPLL was implemented using a 0.9V 32nm practical transistor model (PTM). The simulation results show that the proposed ADPLL achieves 10 and 2 reference cycles of frequency and phase acquisitions at 700 MHz with peak to peak jitter ≪ 67ps.

A novel all-digital phase-locked loop with ultra fast frequency and phase acquisition

In this paper, a low power and low jitter 12-bit CMOS digitally controlled oscillator (DCO) design is presented. The CMOS DCO design is based on a ring oscillator implemented with Schmitt trigger based inverters. Simulations of the proposed DCO using 32 nm predictive transistor model (PTM) achieve controllable frequency range of around 570 MHz~850 MHz with a wide range of linearity. Monte Carlo simulation demonstrates that the time-period jitter due to random power supply fluctuation is under 75 ps and the power consumption is 2.3 mW at 800 MHz and 0.9 power supply.

A low power 32 nanometer CMOS digitally controlled oscillator

/pdf/negative-high-voltage-dc-dc-converter-using-a-new-cross-4ewf07y2su.pdf

Negative High Voltage DC-DC Converter Using a New Cross-Coupled Structure

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