The total ionizing dose response of both CMOS transistors and SiGe HBTs implemented without utilizing any radiation hardening by design techniques in Jazz Semiconductor's SBC-18-HXL BiCMOS technology platform is evaluated. The SiGe HBTs remain functional up to the 6 Mrad (SiO
 2
) dose levels needed to support multi-Mrad exploration missions such as NASA's Europa mission. The CMOS devices are also functional to this extreme total dose. The nFETs exhibit significantly reduced shallow trench isolation leakage compared with nFETs implemented in prior SiGe BiCMOS processes. Both nFETs and pFETs show negligible transconductance and on-current degradation. We conclude that this SiGe process technology is a potential candidate for implementing reliable and survivable multi-Mrad total ionizing dose-hard electronic systems.

Advanced SiGe BiCMOS Technology for Multi-Mrad Electronic Systems

The mechanism for ionizing radiation damage in multi-finger SOI CMOS devices is presented for the first time. We analyzed the effects of shallow-trench isolation on ionizing radiation response of 65 nm Silicon-On-Insulator (SOI) CMOS technology. The radiation response of the CMOS devices was investigated using 63 MeV protons and 10 keV X-rays. The implications of proton irradiation and X-ray irradiation on the dc and RF performance of these devices are presented. The cut-off frequency is degraded due to post-irradiation degradation of device transconductance. Even though there is charge-accumulation in the buried-oxide, there is minimal impact on the front-gate characteristics of the partially-depleted SOI devices in this 65 nm CMOS technology. The implications of parasitic conduction along the STI on device design constraints, particularly for varying device width and number of gate fingers, are discussed in the context of high performance RF CMOS technology. These results suggest that body-contacting schemes which eliminate sidewalls (e.g., H-body, T-body) will provide the necessary total-dose radiation tolerance for multi-finger analog and RF devices, without additional hardening techniques.

The Enhanced Role of Shallow-Trench Isolation in Ionizing Radiation Damage of 65 nm RF-CMOS on SOI

The effects of proton irradiation on the dc and ac properties of 130 nm Si CMOS technology are investigated. The impact of substrate bias is reported for the first time. Two different irradiation substrate conditions were used, yielding different results. A comparison is drawn between the present work and a previously reported 180 nm CMOS technology node.

The impact of substrate bias on proton damage in 130 nm CMOS technology

The effects of 63 MeV proton irradiation on the DC and RF performance of a 0.12 /spl mu/m CMOS technology is presented for the first time. The radiation response of the CMOS devices was investigated up to an equivalent total gamma dose of 1.0 Mrad(Si). Measurements of the DC current-voltage, low-frequency (1/f) noise, S-parameters, and broadband noise characteristics of the devices were performed before and after irradiation at room temperature. These scaled CMOS devices show a very slight degradation of threshold voltage, transconductance (g/sub m/), and 1/f noise after proton irradiation without any intentional radiation hardening. High-frequency measurements on the irradiated devices show that there is very little or no perceptible degradation of S-parameters, cut-off frequency (f/sub T/), or broadband noise characteristics to 1 Mrad(Si) exposure levels. These results suggest that this 0.12 /spl mu/m CMOS technology is well-suited for the development of total-dose radiation tolerant analog and RF circuits without additional radiation hardening.

Impact of proton irradiation on the RF performance of 0.12 /spl mu/m CMOS technology [MOSFET devices]

The effects of 63 MeV proton irradiation on 65nm Silicon-On-Insulator (SOI) CMOS technology are presented for the first time. The radiation response of the CMOS devices was investigated up to an equivalent total gamma dose of 4.1 Mrad (SiO2). We analyze the implications of proton irradiation on RF performance of these devices. The cut-off frequency is degraded due to post-irradiation degradation of device transconductance. High-frequency measurements show that the input and output matching conditions are not affected, up to a cumulative dose of 4.1 Mrad. The implications of proton irradiation on device design constraints, particularly device width and number of gate fingers, are discussed in the context of high performance RF CMOS technology. These results suggest that the higher finger width devices, of sufficient gate width, are well-suited for the development of total-dose radiation tolerant analog and RF circuits without additional radiation hardening.

Impact of Proton Irradiation on the RF Performance of 65 nm SOI CMOS Technology

The paper presents the results of an investigation of the proton tolerance of the multiple-threshold voltage and multiple-breakdown voltage device design points contained in a 0.18 /spl mu/m system-on-a-chip CMOS technology. The radiation response of the CMOS devices having three different device design configurations are characterized and compared for equivalent gamma doses up to 300 krad(Si), using the threshold voltage, off-state leakage, and effective mobility to assess the dc performance. All three CMOS device configurations show a very slight degradation of threshold voltage and effective mobility with increasing dose. We also present for the first time the frequency response and S-parameters of these RF CMOS devices under proton radiation. The S-parameters and cut-off frequency show little degradation up to 300 krad(Si) total dose. These results suggest that the CMOS devices in this 0.18 /spl mu/m SoC CMOS technology are well-suited for RF circuit applications in an ionizing radiation environment without intentional total-dose hardening.

/pdf/proton-tolerance-of-multiple-threshold-voltage-and-multiple-3j66rgfdzp.pdf

Proton tolerance of multiple-threshold voltage and multiple-breakdown voltage CMOS device design points in a 0.18 /spl mu/m system-on-a-chip CMOS technology

Handle everyday research tasks with reliable, citation-backed results

Your personal Research Agent to handle research tasks with citation-backed results

Popular Tasks used by Researchers

How can I help with your research?

Meet SciSpace

Get more enhanced response by uploading the PDFs you want me to reference.

No relevant PDFs in your library

SciSpace is the AI research assistant for academics. Run systematic literature reviews on 280M+ papers, and write papers with cited sources. Trusted by 1M+ students, PhDs & researchers.

SciSpace | AI for Research

Analyze PDFs

Code & Manuscripts

Funding & Grants

Literature & Patents

Medical & Clinical Data

Systematic Review

Visualize & Present

Web & Data

Build a Google Scholar-like website for your research.

Build a website

Create charts and images for your research

Create a Chart

Write a paper for submission to a journal

Draft a manuscript

Patent Search

Design eye-catching scientific posters in minutes.

Scientific Poster Generation

Systematic Literature Review

One task is running at the moment. Your messages will be shown right after.

Drag and drop or click here to browse

Loved by <highlight>1 million+</highlight> researchers

Extract a list of specific topics and their sources from unstructured text

Topics

Compare and analyze relevant papers that matches with your search

Papers

Get insights from PDFs and bookmarked papers from your library

My library

Recent searches

Try searching for:

Catch AI-generated content in scholarly and non-scholarly content

{ai} Detector

Ai Writer

Get PDF Summaries, highlighted text explanations 

Chat with PDF

Effortlessly create in-text citations and bibliographies in APA and 2,500 other formats

Citation generator

Get explanations, summaries, and answers on academic papers

Ease up your research workflow with {scispace}'s cohort of exciting AI tools

Elevate your academic writing skills and convey your ideas the way you want

Paraphraser

Explore our range of reading and writing tools

Your file is being prepared and should be ready in a few minutes. If it's a large file, it might take a bit longer. You can close this window, and we'll email you the file when it's done.

You have reached a maximum limit of <strong>{limit}</strong> columns in the table. Remove at least <strong>1</strong> column to add or create another one.

Jun Pan

Author Tools

Chat about Author

Papers

Proton tolerance of multiple-threshold voltage and multiple-breakdown voltage CMOS device design points in a 0.18 /spl mu/m system-on-a-chip CMOS technology