The fast development of the Internet of things (IoT) promises to deliver convenience to human life. However, a huge amount of the data is constantly generated, transmitted, processed, and stored, posing significant security challenges. The currently available security protocols and encryption techniques are mostly based on software algorithms and pseudorandom number generators that are vulnerable to attacks. A true random number generator (TRNG) based on devices using stochastically physical phenomena has been proposed for auditory data encryption and trusted communication. In the current study, a Bi2O2Se-based memristive TRNG is demonstrated for security applications. Compared with traditional metal–insulator–metal based memristors, or other two-dimensional material-based memristors, the Bi2O2Se layer as electrode with non-van der Waals interface, high carrier mobility, air stability, extreme low thermal conductivity, as well as vertical surface resistive switching shows intrinsic stochasticity and complexity in a memristive true analogue/digital random number generation. Moreover, those analogue/digital random number generation processes are proved to be resilient for machine learning prediction.

Bi2O2Se-Based True Random Number Generator for Security Applications

Machine Learning for Semiconductors

Machine learning (ML)-based compact model (CM) provide an alternative way in contrast to physics-based CMs. The advantages of ML CMs include the process-aware capability, expandability, improved behavioral model for a circuit block, and usability for emerging devices. On the other hand, while ML is on the rise, device physics can provide many guidelines in constructing ML CMs. Here, we propose a physics architecture in ML CMs for resistive random access memory (RRAM). The results show that the physics-assisted architecture enables simpler ML models in reference to our previous work of long short-term memory (LSTM)-based RRAM CMs. We found that the discrete state variable with classification is the best model to describe the RRAM set/reset scenario in multistep prediction problems. For the discrete and continuous state variables, the root mean square error (RMSE) on test data is 0.000125 and 0.000119, respectively. In addition, we demonstrate that the transient behavior of set/reset changes can be easily incorporated into the proposed model. Finally, the Verilog-A and HSPICE on a 1T1R cell have also been shown to prove the model feasibility. We suggest that the uniform framework with hybridization in physics and ML should be the most efficient way in future compact device modeling. The code is available at https://github.com/albertlin11/RRAMunif.

RRAM Compact Modeling Using Physics and Machine Learning Hybridization

By harnessing the physically unclonable properties, true random number generators (TRNGs) offer significant promises to alleviate security concerns by generating random bitstreams that are cryptographically secured. However, fundamental challenges remain as conventional hardware often requires complex circuitry design, showing a predictable pattern that is susceptible to machine learning attacks. Here, a low-power self-corrected TRNG is presented by exploiting the stochastic ferroelectric switching and charge trapping in molybdenum disulfide (MoS2 ) ferroelectric field-effect transistors (Fe-FET) based on hafnium oxide complex. The proposed TRNG exhibits enhanced stochastic variability with near-ideal entropy of ≈1.0, Hamming distance of ≈50%, independent autocorrelation function, and reliable endurance cycle against temperature variations. Furthermore, its unpredictable feature is systematically examined by machine learning attacks, namely the predictive regression model and the long-short-term-memory (LSTM) approach, where nondeterministic predictions can be concluded. Moreover, the generated cryptographic keys from the circuitry successfully pass the National Institute of Standards and Technology (NIST) 800-20 statistical test suite. The potential of integrating ferroelectric and 2D materials is highlighted for advanced data encryption, offering a novel alternative to generate truly random numbers.

https://onlinelibrary.wiley.com/doi/pdfdirect/10.1002/smll.202302842

Attack Resilient True Random Number Generators Using Ferroelectric-Enhanced Stochasticity in 2D Transistor.

It is always highly desired to have a well-defined relationship between the chemistry in semiconductor processing and the device characteristics. With the shrinkage of technology nodes in the semiconductors roadmap, it becomes more complicated to understand the relation between the device electrical characteristics and the process parameters such as oxidation and wafer cleaning procedures. In this work, we use a novel machine learning approach, i.e., physics-assisted multitask and transfer learning, to construct a relationship between the process conditions and the device capacitance voltage curves. While conventional semiconductor processes and device modeling are based on a physical model, recently, the machine learning-based approach or hybrid approaches have drawn significant attention. In general, a huge amount of data is required to train a machine learning model. Since producing data in the semiconductor industry is not an easy task, physics-assisted artificial intelligence has become an obvious choice to resolve these issues. The predicted C–V uses the hybridization of physics, and machine learning provides improvement while the coefficient of determination (R2) is 0.9442 for semisupervised multitask learning (SS-MTL) and 0.9253 for transfer learning (TL), referenced to 0.6108 in the pure machine learning model using multilayer perceptrons. The machine learning architecture used in this work is capable of handling data sparsity and promotes the usage of advanced algorithms to model the relationship between complex chemical reactions in semiconductor manufacturing and actual device characteristics. The code is available at https://github.com/albertlin11/moscapssmtl.

https://pubs.acs.org/doi/pdf/10.1021/acsomega.1c05552

Mapping Oxidation and Wafer Cleaning to Device Characteristics Using Physics-Assisted Machine Learning

With the immense increase in the processing data during the scaling down of semiconductor devices by Moore’s Law, it is in urgent need to use data analytics to meet the state of the art performance in both manufacturing and device compact modeling. In particular, managing the fabrication cost and promptly providing compact device models, especially for new or emerging devices, is challenging. To ease out these issues, we propose a unified, general-purpose, process-aware machine learning (ML) based compact model (CM) for resistive random-access memory (RRAM), and the same methodology can be used for any memory devices with hysteresis. A long short-term memory (LSTM) ML model is used to fit the RRAM current-voltage (I-V) characteristics. The memorizing capability of LSTM ensures one model can fit both RRAM low resistance state (LRS) and high resistance state (HRS). The fitted dataset is based on the fabricated RRAM samples using TaN/HfO2/Pt/Ti/SiO2/Si structure. The resultant fitting error is 0.0096 in sinusoidal wave input voltage and 0.0148 in random walk voltage sequences. In the process-aware demonstration, we use post-oxide annealing dataset from 300°C to 500°C. The root mean squared error (RMSE) in the process-aware RRAM compact model is 0.0028. Thus, the LSTM-based CM has the potential to compete with the conventional compact device models in terms of shorter developing time, better fitting capability in emerging devices and a large number of devices, easily incorporated process-aware models, and one unified model accounting for LRS and HRS ensuring differentiability. We propose that the LSTM based memory CM can be useful in intelligent manufacturing, process tuning, and simulation program with integrated circuit emphasis (SPICE) modeling in circuit simulation.

/pdf/a-process-aware-memory-compact-device-model-using-long-short-3aeqivd88n.pdf

A Process-Aware Memory Compact-Device Model Using Long-Short Term Memory

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A Process-Aware Memory Compact-Device Model Using Long-Short Term Memory

Mapping Oxidation and Wafer Cleaning to Device Characteristics Using Physics-Assisted Machine Learning