Recent Advances in GaN‐Based Power HEMT Devices

Models for calculating the sheet densities of two-dimensional electron gas (2DEG) induced by spontaneous and piezoelectric polarization in AlGaN/GaN, AlGaN/AlN/GaN, and GaN/AlGaN/GaN heterostructures are provided. The detailed derivation process of the expression of 2DEG sheet density is given. A longstanding confusion in a very widely cited formula is pointed out and its correct expression is analyzed in detail.

https://iopscience.iop.org/article/10.1088/1674-1056/24/6/067301/pdf

Formation of two-dimensional electron gas at AlGaN/GaN heterostructure and the derivation of its sheet density expression

Challenges in material processing and reliability issues in AlGaN/GaN HEMTs on silicon wafers for future RF power electronics & switching applications: A critical review

In this letter, we present high-performance GaN-on-Si metal-oxide-semiconductor high electron mobility transistors with record reverse-blocking (RB) capability. By replacing the conventional ohmic drain with a hybrid tri-anode Schottky drain, a high reverse breakdown voltage ( ${V}_{\text {B}}^{\text {R}}$ ) of −900 V was achieved (at $1~\mu \text{A}$ /mm with grounded substrate), along with a small reverse leakage current ( ${I}_{\text {R}}$ ) of ~20 nA/mm at −750 V. The devices also presented a small turn- on voltage ( ${V}_{{ \mathrm{\scriptscriptstyle ON}}}$ ) of 0.58 ± 0.02 V, a small increase in forward voltage ( $\Delta {V}_{\text {F}}$ ) of ~0.8 V, a high ON/OFF ratio over 1010, and a high forward breakdown voltage ( ${V}_{{{\text {B}}}}^{{{\text {F}}}}$ ) of 800 V at 20 nA/mm with grounded substrate. These results demonstrate a new milestone for RB GaN transistors, and open enormous opportunities for integrated GaN power devices.

/pdf/900-v-reverse-blocking-gan-on-si-moshemts-with-a-hybrid-tri-3i4uxq9ue7.pdf

900 V Reverse-Blocking GaN-on-Si MOSHEMTs With a Hybrid Tri-Anode Schottky Drain

High-frequency enhancement-mode (E-mode) AlGaN/GaN high-electron-mobility transistors (HEMTs) with plasma oxidation technology (POT) were fabricated through plasma-enhanced chemical vapor deposition. POT enables the formation of a thin oxide layer in the gate region, which decreases the gate leakage by at least two orders of magnitude compared with conventional recessed gate HEMTs. Ultra-low leakage was achieved in the fabricated device, with Ioff = 9.5 × 10−7 mA/mm and a high ON/OFF ratio of over 109. Good suppression of current collapse was obtained after the application of POT in the access region. The enhancement-mode AlGaN/GaN HEMTs with POT showed an outstanding performance, with a Vth of 0.4 V, a maximum drain current of 965 mA/mm, and an fmax of 272 GHz.

90 nm gate length enhancement-mode AlGaN/GaN HEMTs with plasma oxidation technology for high-frequency application

In this paper, we demonstrate that a Schottky drain can improve the forward and reverse blocking voltages (BVs) simultaneously in AlGaN/GaN high-electron mobility transistors (HEMTs). The mechanism of improving the two BVs is investigated by analysing the leakage current components and by software simulation. The forward BV increases from 72 V to 149 V due to the good Schottky contact morphology. During the reverse bias, the buffer leakage in the Ohmicdrain HEMT increases significantly with the increase of the negative drain bias. For the Schottky-drain HEMT, the buffer leakage is suppressed effectively by the formation of the depletion region at the drain terminal. As a result, the reverse BV is enhanced from −5 V to −49 V by using a Schottky drain. Experiments and the simulation indicate that a Schottky drain is desirable for power electronic applications.

https://iopscience.iop.org/article/10.1088/1674-1056/23/10/107303/pdf

Mechanism of improving forward and reverse blocking voltages in AlGaN/GaN HEMTs by using Schottky drain

In this article, the Au-free complementary metal oxide semiconductor (CMOS) transistor compatible AlGaN-channel high-electron-mobility transistors (HEMTs) on silicon substrate with 2-kV forward and reverse blocking voltages have been reported. Due to the designed AlGaN epitaxial layers, breakdown voltages (BVs) of the conventional AlGaN-channel HEMTs with $L_{GD} =5$ /10/15/ 20/ $25~\mu \text{m}$ are 420/1070/1590/1920/2000 V respectively, and the values are increased to 760/1420/1980/1990/2000 V by using Schottky-drain technique. The reverse-blocking HEMTs demonstrate reverse blocking voltages of −790/−1300/−1810/−2000 V for ${L}_{GD}=5$ /10/15/ $20~\mu \text{m}$ . Meanwhile, the conventional HEMT power figure-of-merit (FOM) of 397 MW/cm2 is the highest FOM for AlGaN-channel HEMTs on silicon, and the Schottky-drain HEMT forward FOM of 384 MW/cm2 and reverse FOM of 321 MW/cm2 are the highest FOM values for all GaN-based reverse-blocking HEMTs on silicon.

Au-Free Al₀.₄Ga₀.₆N/Al₀.₁Ga₀.₉N HEMTs on Silicon Substrate With High Reverse Blocking Voltage of 2 kV

In this work, device parameters for GaN vertical trench MOSFETs have been investigated systematically to further improve the device characteristics. The n− GaN drift layer, the p+ GaN layer and the trench gate are designed and optimized systematically using Silvaco ATLAS 2-D simulation, in order to get the best trade-off between $V_{\mathrm {BR}}$ and specific on-resistance $R_{\mathrm {on}}$ . Three-terminal breakdown curves, the electron concentration, current density and electric field strength distributions have been presented to analyze the breakdown characteristics. The correlations between different parameters and different initial conditions are considered, and the eight parameters are optimized comprehensively. After the final optimization, record high FOM of 4.8 GW/cm2, $V_{\mathrm {BR}}$ of 2783 V, average electric field $E_{\mathrm {drift}}$ of 1.98 MV/cm and a low $R_{\mathrm {on}}$ of 1.6 $\text{m}\Omega \cdot $ cm2 are obtained for drift layer thickness of $14~\mu \text{m}$ . The product of the thickness $L_{\mathrm {p}}$ and doping density $N_{\mathrm {p}}$ of p+ GaN layer can determine the breakdown mechanism, and punch through mechanism would occur when $L_{\mathrm {p}}\cdot N_{\mathrm {p}}$ is lower than a certain value. The results indicate there exists large optimization room for fabricated GaN vertical trench MOSFETs, and the device characteristics can be further improved through the methodology in this paper for high power and high voltage applications.

/pdf/comprehensive-design-of-device-parameters-for-gan-vertical-475e80qhqt.pdf

Comprehensive Design of Device Parameters for GaN Vertical Trench MOSFETs

A novel AlGaN/GaN high electron mobility transistor (HEMT) with double buried p-type layers (DBPLs) in the GaN buffer layer and its mechanism are studied. The DBPL AlGaN/GaN HEMT is characterized by two equi-long p-type GaN layers which are buried in the GaN buffer layer under the source side. Under the condition of high-voltage blocking state, two reverse p-n junctions introduced by the buried p-type layers will effectively modulate the surface and bulk electric fields. Meanwhile, the buffer leakage is well suppressed in this structure and both lead to a high breakdown voltage. The simulations show that the breakdown voltage of the DBPL structure can reach above 2000 V from 467 V of the conventional structure with the same gate-drain length of 8 μm.

https://iopscience.iop.org/article/10.1088/0256-307X/33/6/067301/pdf

Enhancement of Breakdown Voltage in AlGaN/GaN High Electron Mobility Transistors Using Double Buried p-Type Layers

The invention discloses a method for selecting an optimal semiconductor device temperature and humidity combined stress acceleration model The method includes the steps of screening out qualified samples, grouping the qualified samples, conducting normal stress degeneration testing on one of the groups, conducting acceleration degeneration testing on the other five groups, periodically detecting and recording possible sensitive parameters of the samples, determining the sensitive parameters of the tested samples and degeneration track models of the sensitive parameters, conducting extrapolation to obtain the pseudo service life of each tested sample, determining the distribution types of the pseudo service life, conducting fitting to obtain distribution parameters of the distribution types, calculating the average service life of the samples under the normal stress degeneration test and the average service life of the samples under the acceleration stress test, calculating model parameters and acceleration factors of a temperature and humidity combined stress acceleration model to be evaluated, conducting extrapolation to obtain the service life of the samples under the normal temperature and humidity stress condition, comparing the average service life of the samples with the service life, obtained through extrapolation, of the samples, and determining the model with the service life closest to the average service life as the optimal model The method is reasonable in test scheme design, scientific in analysis method and capable of accurately judging the optimal temperature and humidity combined stress acceleration model, and is mainly applied to the field of semiconductor device reliability evaluation

Method for selecting optimal semiconductor device temperature and humidity combined stress acceleration model

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