This article presents a four-element phased-array transceiver (TRX) front-end for millimeter-wave (mm-Wave) 5G new radio (NR). The effects of amplitude-to-phase (AM–PM) and amplitude-to-amplitude (AM–AM) distortions on error vector magnitude (EVM) are detailed. A three-stage highly linear wideband class-AB power amplifier (PA) is described, mitigating AM–PM and AM–AM distortions without degrading other performances. A matching network embedded transmitting/receiving (T/R) switch is proposed to support time division duplex (TDD). With the proposed technique, RF switch insertion losses are reduced in both transmitter (TX) and receiving (RX) modes. In each TRX element, phase and gain controls are achieved by a 6-bit vector-modulated phase shifter (VMPS) with a phase tuning range of 360° and a 6-bit attenuator with a gain tuning range of 31.5 dB, respectively. Fabricated in 65-nm bulk CMOS, the proposed packaged TRX demonstrates the measured peak gains of 25.5/14.2 dB with the gain ripples of less than 2.5/1.9 dB across 24–29.5 GHz in the TX/RX mode. The measured peak <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\text {1 dB}}$ </tex-math></inline-formula> is 17.6 dBm with a power added efficiency (PAE) of 20.4%. The measured minimum noise figure (NF) is 4.3 dB. The TRX achieves an output power of 7.9–8.9 dBm and an EVM of −25 dB with 8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 100-MHz 5G NR frequency range 2 (FR2) orthogonal frequency division multiplexing (OFDM) 64-quadrature amplitude modulation (QAM) signals across 24–29.5 GHz, covering 3rd generation partnership project (3GPP) 5G NR FR2 operating bands (i.e., n257, n258, and n261) around 26 GHz. 

A 24–29.5-GHz Highly Linear Phased-Array Transceiver Front-End in 65-nm CMOS Supporting 800-MHz 64-QAM and 400-MHz 256-QAM for 5G New Radio

We present a broadband parallel-combined compact Doherty power amplifier (PA) in a 28-nm bulk complementary metal–oxide–semiconductor (CMOS) device technology for fifth-generation (5G) millimeter-wave (mm-Wave) frequency band (n257, n258, and n261) applications. The proposed Doherty PA has a single transformer (TF)-based output matching network and an equivalent quarter-wavelength line placed between the carrier and peaking amplifiers, absorbing transistors’ output parasitic capacitances. Therefore, the Doherty PA occupies a very small die area and has a wide bandwidth characteristic compared with the conventional Doherty PA output matching network topologies (e.g., parallel- and series-combined Doherty PA output matching networks). The two-stage differential Doherty PA is implemented, which shows a saturation output power (<inline-formula> <tex-math notation="LaTeX">$P_{\mathrm {OUT}}$ </tex-math></inline-formula>) of >18.8 dBm and a peak power-added efficiency (PAE) of >30% at 27 GHz. It also exhibits a linear <inline-formula> <tex-math notation="LaTeX">$P_{\mathrm {OUT}}$ </tex-math></inline-formula> of 12.4 dBm and an average PAE of 20.2% for 100 MHz 5G NR signal (<inline-formula> <tex-math notation="LaTeX">$P_{\mathrm {OUT}}$ </tex-math></inline-formula> of 11.4 dBm and PAE of 18.1% for 8 <inline-formula> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 100 MHz carriers) at the EVM of −25 dB. Over the frequency range of 24.5–29.5 GHz, the PA achieves a linear <inline-formula> <tex-math notation="LaTeX">$P_{\mathrm {OUT}}$ </tex-math></inline-formula> of >11.2 dBm and a PAE of >14.5% (drain efficiency >20.8%). This PA occupies 640 <inline-formula> <tex-math notation="LaTeX">$\mu \text{m}\,\,\times $ </tex-math></inline-formula> 250 <inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> (core only) and is successfully integrated into a 32-channel RF phased-array transceiver IC for the first time. The IC die area is 10.2 mm <inline-formula> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 6.4 mm and consumes about 120 mW per channel at <inline-formula> <tex-math notation="LaTeX">$P_{\mathrm {OUT}}$ </tex-math></inline-formula> of 10.0 dBm.

Single Transformer-Based Compact Doherty Power Amplifiers for 5G RF Phased-Array ICs

In this article, a load-modulation enhanced wideband compact high-efficiency millimeter-wave (mm-wave) gallium nitride (GaN) monolithic microwave integrated circuit (MMIC) synchronous Doherty power amplifier (DPA) is presented. A synchronous DPA architecture is used to ensure the optimal saturation performance at the mm-wave band. Based on the analysis of load-modulation behavior, the bandwidth of the DPA can be extended by decreasing the phase dispersion factor <inline-formula> <tex-math notation="LaTeX">$\alpha $ </tex-math></inline-formula>. A simple optimal tuning-based method is proposed to design an equivalent <inline-formula> <tex-math notation="LaTeX">$\lambda $ </tex-math></inline-formula>/4 transmission line (EQWTL) with the minimal <inline-formula> <tex-math notation="LaTeX">$\alpha $ </tex-math></inline-formula> for a given topology. Furthermore, the influence of the power division ratio <inline-formula> <tex-math notation="LaTeX">$\sigma $ </tex-math></inline-formula> on the proposed DPA’s load-modulation behavior has also been analyzed and a proper load modulation can be realized by splitting more power to the peaking branch properly. For verification, a 24–28-GHz GaN MMIC synchronous DPA has been designed using a 0.15-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> GaN on silicon carbide high-electron-mobility transistor process. Both the load modulation and the matching of the fundamental and the second harmonic load impedances can be realized by a modified bandpass-type EQWTL with a minimal <inline-formula> <tex-math notation="LaTeX">$\alpha $ </tex-math></inline-formula> easily. Experimental results show that the fabricated DPA can achieve the output power of 35.4–36 dBm and the power-added efficiency (PAE) of 27.8%–36.8% at saturation. The PAE at 6-dB power back-off (PBO) is 18.3%–30.1% and the 9-dB PBO PAE is higher than 14.3% in the whole frequency band. An average PAE of 27.4% with good linearity is obtained when excited by a 400-MHz modulated signal after linearization.

A 24–28-GHz GaN MMIC Synchronous Doherty Power Amplifier With Enhanced Load Modulation for 5G mm-Wave Applications

In this work, we illustrate the roles and requirements of packaging in the implementation of hybrid beamforming-based mmWave massive MIMO architectures for the development of 5G hardware modules and systems.

Roles and Requirements of Electronic Packaging in 5G

Novel linearity enhancement using body bias tuning for 24–28 GHz CMOS SOI power amplifier (PA) design is reported. The differential PA is designed, laid out, and taped out in an advanced 22nm fully-depleted silicon-on-insulator (FD-SOI) technology, which utilizes stacked FETs, digitally-controlled neutralization capacitors, interstage matching and output matching capacitors with on-chip baluns to cover 24–28 GHz for potential 5G applications. Post-layout SPICE simulations show the AM-PM distortion at P out,1dB can be reduced to only out,1dB at 24.1%/17.5% with high S21 =26.5/22.1 dB at 24GHz/28GHz. Using 64-QAM 250 MHz modulated input signal, this PA design has also achieved an ACLR1 of ∼ −24.5/−28.5 dBc at P out = 11.7/9.5 dBm in post-layout simulation at 28 GHz, and with the smallest core PA die area in the literature. We believe this is the 1st report of very effective AM-PM cancellation for mm-Wave CMOS SOI PA design using positive body biasing.

Effective AM-PM Cancellation with Body Bias for 5G CMOS Power Amplifier Design in 22nm FD-SOI

This brief presents a single-ended, two-stage, and symmetric Doherty power amplifier (DPA). A rigorous and closed-form formula is proposed to design the transformer-based quadrature hybrid. The hybrid combines the advantages of flexibility, compactness, and low loss. A non-classic Doherty impedance inverting network is co-designed with the input network for phase matching. Besides, the parasitic parameters of the interconnects and RF pads are used to reduce the value of the inductor in the LC network. Designed and implemented in a 65-nm CMOS process, the fully integrated compact DPA prototype occupies only 0.35 mm2 active area. The experimental prototype operating at 28 GHz achieves 18.7 % power-added efficiency (PAE) at 6-dB power back-off (PBO). A maximum small-signal gain of 20.4 dB is achieved with a −3-dB bandwidth from 25.6 to 29.4 GHz. A saturated output power ( $P_{SAT}$ ) of 17.5 dBm is measured with the peak PAE of 27%. At 6-dB PBO, the DPA prototype increases the efficiency by 2.8 and 1.4 times over a normalized Class-B and Class-A PA, respectively.

A 28-GHz Doherty Power Amplifier With a Compact Transformer-Based Quadrature Hybrid in 65-nm CMOS

This paper reports a fully integrated broadband and linear power amplifier (PA) for 5G phased-array. Weakly-and strongly-coupled transformers are compared and analyzed in detail. The output strongly-coupled transformer is designed to transfer maximum power. The inter-stage weakly-coupled transformer is optimized to broaden the bandwidth. Besides, linearity is highly improved by operating the PA in deep class AB region. Designed and implemented in 65-nm CMOS process with 1V supply, the two-stage PA delivers a maximum small-signal gain of 19 dB. Maximum 1-dB compressed power (P 1dB ) of 17.4 dBm and saturated output power (P SAT ) of 18 dBm are measured at 28 GHz. The power-added efficiency (P AE ) at P 1dB is 26.5%. The measured P 1dB is above 16 dBm from 23 to 32 GHz, covering potential 5G bands worldwide around 28 GHz.

A 28-GHz CMOS Broadband Single-Path Power Amplifier with 17.4-dBm P1dB for 5G Phased-Array

This paper presents a Ka-band neutralized medium power amplifier (PA). The two-stage single-path PA adopts the neutralizing capacitors to increase the stability and three types of transformers to simplify the design of impedance matching networks. The push-pull common-source configuration is employed in each stage to enhance the efficiency. Designed and implemented in 65nm CMOS technology with 1-V supply, the prototype delivers a saturated output power (Psat) of 13 dBm from 27–33 GHz with the maximum small-signal gain of 18 dB. The measured maximum Psat is 13.77 dBm at 30 GHz with corresponding 1dB compression power (P1dB) of 12.67 dBm and power-added efficiency (PAE) of 29.8%. The chip size is only 0.18 mm2 excluding all DC pads.

A Ka-band 65-nm CMOS neutralized medium power amplifier for 5G phased-array applications

This letter presents a 39-GHz phase-inverting variable gain power amplifier (VGPA) for 5G communication. Adopting a Gilbert structure-based variable gain amplifier (VGA) stage, the VGPA realized the dB-linear gain control characteristic as well as 180° phase inversion. At 0°/180° phase states, the 39-GHz VGPA achieves the maximum gain of 38.7/38.9 dB with gain tuning range of 5.6/5.2 dB, respectively. Over 38–43 GHz, the phase inversion error is limited within 5.9°, and the rms phase error is less than 3.6°/2.2°. Meanwhile, with the metal interleaving coplanar transformer matching network, this VGPA achieves 17.7/17.6-dBm Psat and 13.2/13.36-dBm OP1 dB, with the power added efficiency (PAE) of 35%/34.5% and 13.6%/14.4% at the saturation and 1-dB compression points, respectively. Over the gain control states, the OP1 dB fluctuation is less than 0.3 dB. Implemented in a 65-nm CMOS process, the proposed VGPA consumes 150 mW with a chip area of 0.3 mm2.

A 39-GHz Phase-Inverting Variable Gain Power Amplifier in 65-nm CMOS for 5G Communication

In this paper, a 26 GHz two-stage differential CMOS power amplifier (PA) is proposed for 5G communication with 65-nm CMOS process. A differential capacitive-neutralized common source gain cell is used to maintain the stability as well as to boost the gain and output power performance. Meanwhile, to achieve good overall performance, the output and inter-stage impedances of the PA are optimized by balancing the amplifier power gain, power added efficiency (PAE) and output power. A low loss four-way transformer-based power combining network is adopted in this PA to achieve high gain and output power performance. With measurements, the PA achieves a peak gain of 26.4 dB at 26 GHz with a bandwidth from 24.7 to 28.5 GHz. At 1dB compression and saturated points, the PA delivers an output power and PAE of 18.8/22.1 dBm and 15.97/33.26%, respectively. The core chip area without pads is 0.805 mm$^{\mathbf{2}}$.

A 26 GHz Power Amplifier with 26.4 dB Power Gain and 22.1 dBm Output Power in 65 nm CMOS

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