This paper presents a reliability simulation framework based on surrogate modeling. A novel methodology has been developed, which integrates variability analysis with the reliability concepts by employing transistor drain-current surrogate models in terms of crucial process parameters, bias voltages, temperature, and time. Simulation techniques using these models enables exploration of the effects of time-based degradation on analog circuits. The analysis of a differential amplifier at the 65-nm technology node reveals that the dc current is reduced by around 10% in ten years. The tool is used to demonstrate how the biasing structures of analog circuits can be designed to boost aging resilience.

Surrogate-Model-Based Analysis of Analog Circuits—Part II: Reliability Analysis

Non-Gaussian observations such as binary responses are common in some computer experiments. Motivated by the analysis of a class of cell adhesion experiments, we introduce a generalized Gaussian pr...

A Generalized Gaussian Process Model for Computer Experiments With Binary Time Series

Aggressive transistor scaling affects the threshold voltage Vth in two ways: space and time. Transistors on the same die can have different Vth due to random dopant fluctuations (RDFs). On the other hand, Vth of a specific transistor can randomly shift in time due to random position of dangling bonds and random motion of atomic H or H2 molecules in the oxide [negative bias temperature instability (NBTI)]. These two random effects are not totally independent because the dissociation rate of Si-H bonds at the silicon-oxide interface depends on the nonuniform electric field. In this paper, we describe the combined effect of RDF and NBTI on Vth using stochastic differential equation. In this paper, we are able to examine the effect of RDF on critical NBTI parameters such as kf, kr, and temperature and the correlation among these parameters. The efficacy of the proposed model is evaluated by performing Monte Carlo simulations on various transistors under different direct-current stress and obtained distributions for NIT and Vth.

A Three-Dimensional Physical Model for $V_{\rm th}$ Variations Considering the Combined Effect of NBTI and RDF

Accurate detection of nanometer CMOS circuits is one of the most critical issues for tolerating the negative bias temperature instability (NBTI). In this paper, a fully digital on-chip aging detector, which achieves a direct correlation between the threshold voltage degradation ( ${\Delta }$ Vth) and the phase difference, has been proposed. The linear correlation is realized based on our revised Schmitt triggers in which the stressed and the fresh devices are embedded. Moreover, the readout circuit has been designed to count, lock, and output the samples through a parallel-to-serial converter. The main contributions include: 1) good linear correlation between ${\Delta }$ Vth and the pulse width is provided; 2) the measurement resolution can be adjusted by changing the input slope; and 3) the circuits are almost independent to process and voltage due to the symmetrical structure and layout matching. The prototype chip has been fabricated in a 1.1 V, 36-nm CMOS technology. The measured equivalent resolution is 3.4 ns/mV under $1~{\mu }\text{s}$ rise-time sawtooth input, which is sufficient to suppress the unwanted recovery. Compared with the traditional testing, the proposed detector can satisfy the surveillance of NBTI degradation. This flexible architecture can be easily revised to accommodate other aging mechanisms, such as PBTI and HCI.

Linear and Resolution Adjusted On-Chip Aging Detection of NBTI Degradation

The trend in microelectronics to reduce device dimensions leads to increasing and new aging effects in the devices. This requires a continuous optimisation of the fabrication process as well as a degradation aware circuit design, to guarantee a high reliability of the functional elements and maintain the stable function of the system. This work focuses on the very sensitive analog circuits. Previous investigations had presented heterogeneous results. Therefore, a throughout and universal study, investigating the impact of several different aging effects on the analog circuitry, had to be performed. This work identifies highly aging sensitive circuit blocks and demonstrates the impact of device wear-out on their performance characteristics with particularly developed models and experiments. Furthermore, universal methodologies for accelerated stress measurements, aging suppression and design guidelines are proposed and evaluated.

/pdf/device-aging-in-analog-circuits-for-nanoelectronic-cmos-25l2fdtlnc.pdf

Device Aging in Analog Circuits for Nanoelectronic CMOS Technologies

In this paper, an effective and efficient methodology for reliability simulation is developed to bridge the gap between device-level reliability and that at product level. For the first time, reliability and circuit-failure behaviors under analog and mixed-signal operating conditions are simulated and analyzed with a high-speed Flash analog-to-digital converter (ADC) circuit developed in advanced CMOS technology. We demonstrate how the failure rate at circuit-level integrating multiple failure mechanisms is determined as a function of operating voltage and temperature. The results show that the dominant failure mechanism and failure rate could be changed by operating conditions. Based on the complete analysis of the ADC circuit operating under normal condition, negative bias temperature instability (NBTI) is the predominant failure mechanism in normal analog and mixed-signal applications, and failure rate increases with the elevated temperature. The impact of NBTI on circuit performance is addressed in detail. Two different types of degradation caused by NBTI are investigated: output voltage degradation and delay. The simulation results are verified by the field data. After exploring the reliability behaviors, a design for reliability methodologies is proposed and classified into two categories: device and circuit levels. This paper shreds light for the circuit life estimation and further reliable design.

Reliability Simulation and Circuit-Failure Analysis in Analog and Mixed-Signal Applications

For the first time, a high speed flash ADC is developed for reliability analysis and simulation of analogue and mix-signal circuit. All the three failure mechanisms (NBTI, HCI, TDDB) are quantified with degradation models. The result shows that pMOS degradation especially NBTI is the most detrimental failure mechanism for the normal operation of high speed ADC, which leads to the fault output. Based on the analysis of the reliability-critical parts, reliability improvement approaches are suggested for the reliable design.

Reliability Simulation and Design Consideration of High Speed ADC Circuits

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Reliability Simulation and Circuit-Failure Analysis in Analog and Mixed-Signal Applications

Reliability Simulation and Design Consideration of High Speed ADC Circuits