Studies of the properties and characteristics of transition metal silicides have been stimulated by their (potential) use in integrated circuit technology. This review describes some of the most recent studies in this field of research. Formation mechanisms of silicides are discussed in some detail. A division is made between near-noble and refractory metal silicidation which aids in the understanding of differences in formation mechanisms of the various silicides. The evolution of the components of thin film stress during metal silicidation is also elucidated. In the review of the practical uses of these materials, emphasis is placed on specific processes involving laterally confined (self-aligned) silicide film formation as more advanced applications require film formation only in certain localized regions on a Si wafer.

https://iopscience.iop.org/article/10.1088/0034-4885/56/11/002/pdf

Transition metal silicides in silicon technology

A review of thin-film aluminide formation

Some of the trends in integrated circuit process development are described. The motivations or technical reasons for this activity are discussed. This effort will continue to develop the downsizing that increases functional density and performance. Limiting factors are examined and new technical developments that could enable CMOS density to be comparable with NMOS density are explored. Various isolation techniques are described and the influence on performance of well profiles and doping concentrations are examined. These trends have a beating on the choice of gate electrode materials. Reliability factors governing the gate dielectric thickness are discussed briefly. MOSFET diode capacitance is shown to be the predominant limiting factor at the device level. Methodologies that could be used to reduce device parasitics are considered in detail. Device scaling below 1-µm calls for changes in contact metallization techniques. Trends in metallization technology and the various methods of fabricating multilevel interconnections when the via sizes become very small are described. The processing methods being investigated to overcome device limitations are examined and compared. In some cases, the present technical difficulties of these methods are discussed. The general conclusion of this work is that "downsizing" will continue, but advances will be more dependent upon innovative processes and device research, whereas in the past, scaling rules were adequate and progress was evolutionary.

Trends in advanced process technology&#8212;Submicrometer CMOS device design and process requirements

A high-performance silicided amorphous-silicon contact and interconnect technology (HPSAC) for VLSI is presented. In this novel scheme, a patterned silicide layer is used to form self-aligned contacts to the source/drain regions, as well as to interconnect devices. The fabrication procedures and some key processing techniques are described, Experimental results on n-and p-channel MOSFET's fabricated with HPSAC technology are presented. The performance improvement due to reduction of parasitic capacitance and resistance is discussed.

HPSAC&#8212;A silicided amorphous-silicon contact and interconnect technology for VLSI

Molybdenum oxide (Mo1−xOx) films were prepared by reactive rf sputtering of a Mo target in O2/Ar plasma. The dependence of film properties on various sputtering parameters is investigated. The atomic percentage of oxygen (x) in the Mo1−xOx films decreases with sputtering power and increases with the partial pressure of oxygen. Mo1−xOx films that exhibit metallic conductivities can be obtained over a wide range of sputtering conditions. The intrinsic film stress of conducting Mo1−xOx is compressive. Such M1−xOx films were shown by backscattering spectrometry to be excellent diffusion barriers between Al and Si up to 600 °C annealing for 30 min.

Properties of reactively sputtered Mo1−xOx films

Thin metal films of Cr, Ti, Mo, and W–Ti (10 wt.%) have been investigated for their effectiveness in preventing the Al–PtSi reaction which occurs during the post‐metallization alloy treatment of Ohmic contacts and Schottky diodes on integrated circuits. The metal films were deposited by two different dc magnetron sputtering systems. The processed structures were compared for their electrical and metallurgical stability as a function of alloy temperature up to 550 °C for 30 min, as well as for effects of a sputter‐etch versus a wet chemical dip prior to the barrier metal and aluminum alloy deposition. Degradation of the electrical behavior of the contact structures at the higher alloying temperatures is correlated with structural alterations of the layered structures by MeV He ion backscattering and Auger electron spectroscopy with Ar ion sputter‐depth profiling. Conditions under which each barrier metal is useful are presented.

Thermal stability of diffusion barriers for aluminum alloy/platinum silicide contacts

We have examined the thermal stability of Al–Si/TiSi2/Si Schottky diodes both with and without a sputter‐deposited W–Ti (10 wt. %) diffusion barrier after furnace annealing up to 550 °C, 30 min. The diodes having the diffusion barrier exhibit stable Schottky barrier heights up to 550 °C, 30 min. In contrast, after 450 °C, 30 min annealing, diodes which do not have a diffusion barrier exhibit Schottky barrier heights typical of Al/n‐Si. Metallurgical interactions have been investigated by He backscattering spectroscopy which shows a stable W–Ti/TiSi2 interface up to 550 °C, 30 min annealing in samples having the diffusion barrier. The samples without a diffusion barrier show evidence of Al–Ti interdiffusion after 450 °C, 30 min annealing. Residual gas incorporation in the barrier layers was investigated by Ar ion sputter‐depth profiling Auger electron spectroscopy. Sheet resistance measurements and x‐ray diffraction analysis were used to investigate intermetallic phase formation. Selective wet etching comb...

Thermal stability of Al–Si/TiSi2/Si Schottky diodes

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Thermal stability of diffusion barriers for aluminum alloy/platinum silicide contacts

Thermal stability of Al–Si/TiSi2/Si Schottky diodes