The efficient hardware implementation of residue number system (RNS) architectures has evolved based on the development of integrated circuit technology. The implementation of RNS adders is discussed in this paper. Three approaches (the binary adder, the look-up table, and the hybrid implementation) are analyzed in the scope of VLSI criteria where the performance measures are area and time. Two layout design procedures have been used. They are flexible and support any type of moduli. The implementation complexity depends on the form and size of the modulus, but, in general, the look-up table approach is preferable in both area and time for moduli up to five bits, while the binary adder and the hybrid approaches offer better performance for larger moduli.

A VLSI implementation of residue adders

In spite of rapid advances during the last few years in the design and realization of digital filters, very little attention has been given to the problems of error detection and correction in digital filters. This paper describes how redundant residue number system properties can be used for this purpose. The theory is presented with special emphasis on overflow detection, error correction, and gradual system degradation in the presence of recurring errors. A filter simulation program is described and simulation results are presented to illustrate the principles in recursive digital filters.

Redundant residue number systems for error detection and correction in digital filters

This paper discusses a technique for multiplying numbers, modulo a prime number, using look-up tables stored in read-only memories. The application is in the computation of number theoretic transforms implemented in a ring which is isomorphic to a direct sum of several Galois fields, parallel computations being performed in each field.

Implementation of Multiplication, Modulo a Prime Number, with Applications to Number Theoretic Transforms

Residue Number Systems (RNS) are proved to be useful in many applications, as for example in signal processing. In this paper, a VLSI computing architecture is proposed for converting an integer number N from the weighted binary representation into and out a residue code based on s moduli. For this architecture a possible layout is given and its complexity is evaluated in terms of area and time. Under several hypotheses on RNS parameters, constructive upper bounds ranging from 0(n^{2} \log n) to 0(n^{2} \log \log n) and from 0(\log^{2} n) to 0(\log n) for area and time, respectively, have been obtained for the direct conversion. On the contrary, constructive upper bounds A = 0(n^{2} \log n) and T = 0(\log^{2} n) have been found independent of the formed hypotheses, for the reverse conversion.

A VLSI algorithm for direct and reverse conversion from weighted binary number system to residue number system

It is known that RNS VLSI processors can parallelize fixed-point addition and multiplication operations by the use of the Chinese remainder theorem (CRT). The required modular operations, however, must use specialized hardware whose design and implementation can create several problems. In this paper a modified residue arithmetic, called pseudo-RNS is introduced in order to alleviate some of the RNS problems when digital signal processing (DSP) structures are implemented. Pseudo-RNS requires only the use of modified binary processors and exhibits a speed performance comparable with other RNS traditional approaches. Some applications of the pseudo-RNS to common DSP architectures, such as multipliers and filters, are also presented in this paper. They are compared in terms of the area-time square product versus other RNS and weighted binary structures. It is proven that existing combinatorial or look-up table approaches for RNS are tailored to small designs or special applications, while the pseudo-RNS approach remains competitive also for complex systems. >

Fast combinatorial RNS processors for DSP applications

Over the last two decades there has been considerable interest in the implementation of digital computer elements using hardware based on the residue number system. This paper considers implementing such systems with arrays of look-up tables placed in high density read-only memories. The type of system discussed is restricted to one in which the only operations are addition, subtraction, multiplication, and scaling by a predetermined constant. Special attention is given to the scaling algorithm, and two different scaling algorithms are developed.

Residue Number Scaling and Other Operations Using ROM Arrays

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Residue Number Scaling and Other Operations Using ROM Arrays

Implementation of Multiplication, Modulo a Prime Number, with Applications to Number Theoretic Transforms