Anti‐ambipolar heterojunctions are vital in constructing high‐frequency oscillators, fast switches, and multivalued logic (MVL) devices, which hold promising potential for next‐generation integrated circuit chips and telecommunication technologies. Thanks to the strategic material design and device integration, anti‐ambipolar heterojunctions have demonstrated unparalleled device and circuit performance that surpasses other semiconducting material systems. This review aims to provide a comprehensive summary of the achievements in the field of anti‐ambipolar heterojunctions. First, the fundamental operating mechanisms of anti‐ambipolar devices are discussed. After that, potential materials used in anti‐ambipolar devices are discussed with particular attention to 2D‐based, 1D‐based, and organic‐based heterojunctions. Next, the primary device applications employing anti‐ambipolar heterojunctions, including anti‐ambipolar transistors (AATs), photodetectors, frequency doublers, and synaptic devices, are summarized. Furthermore, alongside the advancements in individual devices, the practical integration of these devices at the circuit level, including topics such as MVL circuits, complex logic gates, and spiking neuron circuits, is also discussed. Lastly, the present key challenges and future research directions concerning anti‐ambipolar heterojunctions and their applications are also emphasized.

Anti-Ambipolar Heterojunctions: Materials, Devices, and Circuits.

The history of ternary adders goes back to more than 6 decades ago. Since then, a multitude of ternary full adders (TFAs) have been presented in the literature. This article conducts a review of TFAs so that one can be familiar with the utilised design methodologies and their prevalence. Moreover, despite numerous TFAs, almost none of them are in their simplest form. A large number of transistors could have been eliminated by considering a partial TFA instead of a complete one. According to our investigation, only 28.6% of the previous designs are partial TFAs. Also, they could have been simplified even further by assuming a partial TFA with an output carry voltage of 0 V or VDD. This way, in a single-VDD design, voltage division inside the Carry generator part would have been eliminated and less power dissipated. As far as we have searched, there are only three partial TFAs with this favourable condition in the literature. Additionally, most of the simulation setups in the previous articles are not realistic enough. Therefore, the simulation results reported in these papers are neither comparable nor entirely valid. Therefore, the authors got motivated to conduct a survey, elaborate on this issue, and enhance some of the previous designs. Among 84 papers, 10 different TFAs (from 11 papers) are selected, simplified, and simulated in this article. Simulation results by HSPICE and 32 nm carbon nanotube FET technology reveal that the simplified partial TFAs outperform their original versions in terms of delay, power, and transistor count. 

https://onlinelibrary.wiley.com/doi/pdfdirect/10.1049/cds2.12152

Comprehensive survey of ternary full adders: Statistics, corrections, and assessments

Instead of the current method of transmitting voltage or current signals in electronic circuit operation, light offers an alternative to conventional logic, allowing for the implementation of new logic concepts through interaction with light. This manuscript examines the use of light in implementing new logic concepts as an alternative to traditional logic circuits and as a future technology. This article provides an overview of how to implement logic operations using light rather than voltage or current signals using optoelectronic materials such as 2D materials, metal-oxides, carbon structures, polymers, small molecules, and perovskites. This review covers the various technologies and applications of using light to dope devices, implement logic gates, control logic circuits, and generate light as an output signal. Recent research on logic and the use of light to implement new functions is summarized. This review also highlights the potential of optoelectronic logic for future technological advancements.

Contributions of Light to Novel Logic Concepts Using Optoelectronic Materials.

The history of ternary adders goes back to more than six decades ago. Since then, a multitude of ternary full adders (TFAs) have been presented in the literature. This paper aims to conduct a survey to be familiar with the utilized design methodologies and logic families and their prevalence. Although the number of papers about this topic is high, almost none of the previously presented TFAs are in their simplest form. A large number of transistors could have been eliminated by considering a partial TFA instead of a complete one. Moreover, they could have been simplified even further by assuming a partial TFA where the voltage of the output carry is either 0V or VDD. This way, less static power would be dissipated. Therefore, a strong motivation is to correct and enhance the previous designs. Furthermore, different simulation setups, which are not realistic enough, have been taken into account. Therefore, the simulation results reported in the previous papers are neither comparable nor entirely valid. Among the 75 papers in which a new design of TFA has been given, 11 papers are selected, simplified, and simulated in this paper. Simulations are carried out by HSPICE and 32nm CNFET technology while considering a standard test-bed and a complete input pattern to reveal the maximum cell delay. The simplified partial TFAs outperform their original versions in delay, power, and transistor count.

Comprehensive Survey of Ternary Full Adders: Statistics, Corrections, and Assessments

Convolutional Neural Networks (CNN) has gained much attention for the solution of numerous vision problems including disparities calculation in stereo vision systems In this paper, we present a CNN based solution for disparities estimation that builds upon a basic module (BM) with limited range of disparities that can be extended using various BM in parallel Our BM can be understood as a segmentation by disparity and produces an output channel with the memberships for each disparity candidate, additionally the BM computes a channel with the out–of–range disparity regions This extra channel allows us to parallelize several BM and dealing with their respective responsibilities We train our model with the MPI Sintel dataset The results show that ModuleNet, our modular CNN model, outperforms the baseline algorithm Efficient Large-scale Stereo Matching (ELAS) and FlowNetC achieving about a 80% of improvement

/pdf/modulenet-a-convolutional-neural-network-for-stereo-vision-4k6g4tdbl8.pdf

ModuleNet: A Convolutional Neural Network for Stereo Vision

Ternary logic is said to become the potential solution to overcome the issues we encounter in binary systems. To enlighten this potential, we propose a ternary logic based on novel Anti-ambipolar transistors (AATs) and PMOSs. Conventional AATs require a complex fabrication process, and their operation is beyond the range of typical CMOS (>5 $V$). However, Inkjet-printed AATs are easy to fabricate, and their operating voltage is under 2V. Thus, Inkjet-based AATs are highly-suitable to use with other printable devices. Therefore, in this paper, we propose a set of novel ternary logic based on printed AATs and carbon-nanotube PMOSs. With these AATs and PMOSs, we propose 10 novel logic gates that include a practical balanced ternary full adder (TFA). Our TFA presents a compact design that can be implemented only with 41 PMOSs and 17 AATs. Our TFA reduces transistor count by −22.6% compared to the latest TFA design. We highlight that our ternary logic cells based on AATs and PMOSs are 1) the most compact design in terms of transistor count and 2) very convenient to fabricate.

A Convenient Implementation of the Ternary Logic: Using Anti-Ambipolar Transistors and PMOS Based on Printed Carbon Nanotubes

We propose a cost effective depth estimation method using stereo camera and convolutional neural networks for SLAM algorithm. Convolutional neural networks outperform the traditional computer vision approaches in estimating depth of stereo image pairs. However, the performance gain of neural networks approach causes substantial increase in computation cost, which consequently decreases the operation time of mobile robots like domestic robots. To alleviate the high computation problem, this paper proposes quantized shallow Siamese convolutional neural networks which compute the similarity between patches of rectified stereo image pairs to estimate depth. Quantization of weights and reduction of layers in the neural networks can degrade the performance. To mitigate the performance degradation, this paper initially maximizes networks performance with three different methods of batch-normalization, optimal negative matching similarity training, and retraining with a global loss function. Then, the final retrained network is nonuniformly quantized. This non-uniform quantization provides efficient computation with the minimum performance loss. The final quantized shallow Siamese networks achieve 3.29% error rate for KITTI 2012.

A cost effective estimation of depth from stereo image pairs using shallow siamese convolutional networks

MoS2 crystals grown by chemical vapor deposition are suited for realization of practical 2D semiconductor-based electronics. In order to construct complementary circuits with n-type MoS2, another p-type semiconductor, whose performance can be adjusted corresponding to that of MoS2 in the limited chip area, has to be sought. Herein, we present a method for tuning switching threshold voltages of complementary inverters simply via inkjet printing without changing their channel dimensions. Random networks of inkjet printed single-walled carbon nanotubes are formed as p-channels beside MoS2, and their density and thickness are controlled by varying the number of printed layers. As a result, p-type transistor characteristics as well as inverter characteristics are facilely tuned only by varying the number of printed layers.

Shift of switching threshold in low-dimensional semiconductor-based complementary inverters via inkjet printing

Single-walled carbon nanotubes (SWCNTs) have gained much attention as a promising semiconducting nanomaterial in the field of electronic, optical, and photonic applications. In order to implement such applications in the form of wearable devices, inkjet printing technology has shown great promise for cost-effective, large-area device fabrication. In designing electrical circuits, however, dissimilar n-type semiconductors are often required because SWCNTs typically exhibit p-type behavior. This may result in the addition of complex fabrication steps and more areal footprint to match the performance imbalance between two dissimilar semiconductors. Herein, we report a facile route to the fabrication of inkjet-printed p-type SWCNT transistor-based inverters, in which their transistor modes can be simply tuned from enhancement mode to depletion mode by increasing the number of printed SWCNT layers. The threshold voltage shift was systematically obtained by increasing the printing counts of SWCNTs in the channel area. With this transistor-mode-change strategy, a high gain inverter-based amplifier circuit is realized to monitor real-time biosignals, including the chest movement during breathing and muscular movement by a hand gesture. 

Facile Route to Inkjet Printed Carbon Nanotube-Based Inverters with High Gain for Biosignal Monitoring

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A Convenient Implementation of the Ternary Logic: Using Anti-Ambipolar Transistors and PMOS Based on Printed Carbon Nanotubes

A cost effective estimation of depth from stereo image pairs using shallow siamese convolutional networks

Shift of switching threshold in low-dimensional semiconductor-based complementary inverters via inkjet printing

Facile Route to Inkjet Printed Carbon Nanotube-Based Inverters with High Gain for Biosignal Monitoring