Jose A. Tierno
IBM
88 Papers
1.1K Citations
Jose A. Tierno is an academic researcher from IBM. The author has contributed to research in topics: Phase-locked loop & CMOS. The author has an hindex of 24, co-authored 88 publications. Previous affiliations of Jose A. Tierno include California Institute of Technology & Apple Inc..
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Papers
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons
Jae-sun Seo,Bernard Brezzo,Yong Liu,Benjamin D. Parker,Steven K. Esser,Robert K. Montoye,Bipin Rajendran,Jose A. Tierno,Leland Chang,Dharmendra S. Modha,Daniel J. Friedman +10 more
- 20 Oct 2011
TL;DR: A new architecture is proposed to overcome scalable learning algorithms for networks of spiking neurons in silicon by combining innovations in computation, memory, and communication to leverage robust digital neuron circuits and novel transposable SRAM arrays.
408
A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI
TL;DR: An all static CMOS ADPLL fabricated in 65 nm digital CMOS SOI technology has a fully programmable PID loop filter and features a third order delta sigma modulator as discussed by the authors.
200
Active management of timing guardband to save energy in POWER7
Charles R. Lefurgy,Alan J. Drake,Michael Stephen Floyd,Malcolm S. Allen-Ware,Bishop Brock,Jose A. Tierno,John B. Carter +6 more
- 03 Dec 2011
TL;DR: During better-than-worst case conditions the guardband management mechanism reduces the average voltage setting 137–152 mV below nominal, resulting in average processor power reduction of 24% with no performance loss while running industry-standard benchmarks.
154
Introducing the Adaptive Energy Management Features of the Power7 Chip
Michael Stephen Floyd,Malcolm S. Allen-Ware,Karthick Rajamani,Bishop Brock,Charles R. Lefurgy,Alan J. Drake,Lorena Pesantez,Tilman Gloekler,Jose A. Tierno,Pradip Bose,Alper Buyuktosunoglu +10 more
TL;DR: Power7 implements several new adaptive power management techniques which, in concert with the EnergyScale firmware, let it proactively exploit variations in workload, environmental conditions, and overall system use to meet customer-directed power and performance goals.
127
Patent
Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices
Daniel Friedman,Seongwon Kim,Chung H. Lam,Dharmendra S. Modha,Bipin Rajendran,Jose A. Tierno +5 more
- 30 Sep 2010
TL;DR: In this paper, the authors describe a neuromorphic network consisting of a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the neurons via axon paths, dendrite paths and membrane paths.
78