Jongseok Choi
Pusan National University
38 Papers
225 Citations
Jongseok Choi is an academic researcher from Pusan National University. The author has contributed to research in topics: Multiplication & Elliptic curve cryptography. The author has an hindex of 8, co-authored 38 publications. Previous affiliations of Jongseok Choi include University of Luxembourg.
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Papers
Secure IoT framework and 2D architecture for End-To-End security
TL;DR: A new IoT framework to satisfy the End-To-End security feature under the CoAP communication is proposed and encrypts sensitive data by a symmetric encryption and an attribute-based encryption for efficiencies of communication and computation costs.
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Multi-precision Squaring for Public-Key Cryptography on Embedded Microprocessors
Hwajeong Seo,Zhe Liu,Jongseok Choi,Howon Kim +3 more
- 07 Dec 2013
TL;DR: The novel and flexible SBD method, which delays the doubling process till the very end of the partial-product computation and then doubles the result by simply shifting it one bit to the left, outperforms state-of-the-art implementations by a factor of between 3.5% and 4.4%.
A fast ARX model-based image encryption scheme
TL;DR: A novel ARX model-based image encryption scheme that uses addition, rotation, and XOR as its confusion and diffusion mechanism instead of S-Box and permutation as in SP networks is proposed.
Montgomery Modular Multiplication on ARM-NEON Revisited
Hwajeong Seo,Zhe Liu,Johann Großschädl,Jongseok Choi,Howon Kim +4 more
- 03 Dec 2014
TL;DR: The Cascade Operand Scanning (COS) method is introduced to speed up multi-precision multiplication on SIMD architectures and it is shown that two COS computations can be “coarsely” integrated into an efficient vectorized variant of Montgomery modular multiplication, which the paper calls CICOS method.
Compact Implementations of LEA Block Cipher for Low-End Microprocessors
Hwajeong Seo,Zhe Liu,Jongseok Choi,Taehwan Park,Howon Kim +4 more
- 20 Aug 2015
TL;DR: In this article, the authors further improved 128-, 192-and 256-bit LEA encryption for low-end embedded processors by splitting a 32-bit word operation into four byte-wise operations and avoiding several rotation operations by taking advantage of efficient bytewise rotations.