Jon Wade

TL;DR: The design, implementation, and experimental results for a ternary content addressable search engine chip, known as the Database Accelerator (DBA), are discussed and the timing and control methodology, which simultaneously satisfies the complexity, speed, and robustness requirements of the DBA chip, are reported.

TL;DR: In this paper, a clock buffer circuit that generates a local clock signal in response to a system clock signal was proposed, where the buffer control circuit provides a variable delay so that the local clock signals have a selected phase relationship in relation to the system clock signals.

TL;DR: In this article, a massively parallel computer includes a plurality of processing nodes and at least one control node interconnected by a network, which faciliates the transfer of data among the processing nodes.

TL;DR: This paper proposes a complete set of systems thinking skills for use across many different disciplines, with particular emphasis on the ability to assess each of the skills quantitatively, a comprehensible description of the Skills, and the completeness of the set.