John Zolnowsky
Motorola
27 Papers
889 Citations
John Zolnowsky is an academic researcher from Motorola. The author has contributed to research in topics: Word (computer architecture) & Motorola 68851. The author has an hindex of 19, co-authored 27 publications.
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Papers
Patent
Memory management unit
John Zolnowsky,Charles L. Whittington,William M. Keshlear +2 more
- 14 Dec 1981
TL;DR: In this article, an improved associative memory circuit is proposed to detect mapping conflicts between new segment descriptors and existing descriptors, and to prevent the storage of such conflicting segments descriptors.
83
Patent
Data processor which can repeat the execution of instruction loops with minimal instruction fetches
John Zolnowsky,Douglas B. MacGregor,Kim Eckert +2 more
- 17 Oct 1983
TL;DR: In this paper, a pipelined data processor automatically retrieves the stored state information and restores the state thereof in accordance with the retrieved state information, then resumes execution of the instruction.
74
Patent
Virtual machine data processor
Marvin A. Mills,William C. Moyer,Douglas B. MacGregor,John Zolnowsky +3 more
- 17 Oct 1983
TL;DR: In this paper, the authors propose a data processor capable of automatically storing in an external memory all essential information relating to the internal state thereof upon the detection of an access fault during instruction execution.
68
Patent
A method and apparatus for coordinating execution of an instruction by a coprocessor
John Zolnowsky,Gruess Michael,David S. Mothersole,Stanley E. Groves,Douglas B. MacGregor,Van B. Shahan,Donald L. Tietjen +6 more
- 26 Mar 1984
TL;DR: In this article, a system for interfacing a Processor to a Coprocessor using standard bus cycles is presented, where the Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coproprocessor designated by a CopROcessor Identity field in the operation word.
60
Patent
Coprocessor instruction format
Douglas B. MacGregor,John Zolnowsky,David S. Mothersole +2 more
- 18 Sep 1987
TL;DR: In this article, a system for interfacing a Processor to a Coprocessor using standard bus cycles is presented, where the Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coproprocessor designated by a CopROcessor Identity field in the operation word.
58