SIMD paradigm enhances cost and power efficiency of instruction set processors when the executed workload contains appropriate data level parallelism. In this paper, we investigate development of a SIMD ASIP for an HSDPA equalizer receiver for mobile handsets. The ASIP is based on a vector processor template with C-based programming interface. The template is enhanced to capture the 14.4Mbps HSDPA equalizer receiver functionality of the wireless modem. The solution provides improved flexibility compared to the conventional approach while requiring only modest design effort. The template and the design approach can be utilized also for other subsets of modem baseband.

Implementation of an HSDPA Receiver with a Customized Vector Processor

Advanced Encryption Standard (AES) maintains safety and is used for providing security since publishing date. At the present day, crypto devices are produced in order to be smaller and faster. So, AES chips should not only use very small area, but also have enough throughput. In this paper, we present an 8-bit implementation of the AES algorithm which encrypts plaintext with 14.3 Mbps throughput and lays on 4300 GE on ASIC and 299 slices on FPGA devices. We use only one s-box and a quarter mix column modules as significant points.

Design of new tiny circuits for AES encryption algorithm

Application-specific instruction set processor (ASIP) has been considered as a good candidate for embedded system design in the past decade. Major research effort has been devoted to customized configuration and instruction set extension for performance improvement with the area constraint. Recent research has taken power consumption and energy efficiency as the second metric, which is critical for embedded and portable devices. However, as the technology scales, power density increases and hence thermal issue has emerged as another critical concern in nanometer circuit designs. In this paper, we factor in the thermal consideration during ASIP synthesis process, and explore the relationship and trade-offs among three dimensions: performance, energy, and temperature. Both the theoretical analysis and the real design implementations of several example custom processors have demonstrated the importance of thermal-aware ASIP synthesis. To the best of our knowledge, this is the first thermal-aware design methodology for ASIPs.

Thermal-aware Design Considerations for Application-Specific Instruction Set Processor

This paper presents a novel architectural mechanism and a power management structure for the design of an energy-efficient gigabit Ethernet controller. Key characteristics of such a controller are low-latency and high-bandwidth required to meet the pressing demands of extremely high frame and control data, which in turn cause difficulties in managing power dissipation. We propose a flow-through-queue (FTQ) based power management method, which allows some of the tasks involved in processing the frame data to be offloaded. This in turn enables utilization of multiple clock rates and multiple voltages for different cores inside the Ethernet controller. A modeling approach based on semi-Markov decision process (SMDP) and queuing models is employed, which allow one to apply mathematical programming formulations for energy optimization under performance constraints. The proposed gigabit Ethernet controller is designed with a 130nm CMOS technology that includes both high and low threshold voltages. Experimental results show that the proposed power optimization method can achieve system-wide energy savings under tighter performance constraints.

http://www.cecs.uci.edu/~papers/aspdac07/pdf/p571_6B-1.pdf

Flow-Through-Queue based Power Management for Gigabit Ethernet Controller

Selbstschutz in Organic- und Ubiquitous-middleware-Systemen unter Verwendung von Computer-Immunologie.

Configurable processors enable dramatic gains in energy efficiency, relative to traditional fixed instruction-set processors This energy advantage comes from three improvements First, configuration of the instruction set permits a much closer fit of the processor to the target applications, reducing the number of execution cycles required Second, configuring the processor removes unneeded features, reducing power and area overhead Third, automatic processor generation tools enable logic optimization, signal switching reductions, and seamless mapping into low-voltage circuits and processes, for very low-power operation The first improvement has been well-studied Analysis of the second and third improvements requires detailed circuit and layout experiments, which is the primary focus of this paper Starting from a range of existing available power saving options, this work explores the tradeoff and analyzes the results: the design priority tradeoff, the process technology impact, and implementing low-power configurable processor using commercial scaled-VDD cell libraries compatible with mainstream SOC practices These real processor designs can achieve power dissipation approaching 20/spl mu/W/MHz at 08V and close to 10/spl mu/W/MHz at 06V, using production 013/spl mu/m libraries Finally, this work quantifies the dramatic process, voltage and temperature dependence in post-layout leakage power for small processor designs

/pdf/implementing-low-power-configurable-processors-practical-2nwl81c3f7.pdf

Implementing low-power configurable processors: practical options and tradeoffs

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Implementing low-power configurable processors: practical options and tradeoffs