In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.

Method of manufacturing semiconductor integrated circuit device having capacitor element

A method of manufacturing a semiconductor device includes a monocrystalline semiconductor layer of one conductivity type with a first insulating film covering the semiconductor layer. An aperture is selectively formed in the first insulating film to expose a part of the semiconductor layer. A first polycrystalline semiconductor film of an opposite conductivity type is formed on the first insulating film and has an overhang portion projecting over the aperture from an edge of the first insulating film defining the aperture. A second polycrystalline semiconductor film and a monocrystalline semiconductor film of the opposite conductivity type are grown simultaneously on a bottom surface of the overhang portion of the first polycrystalline semiconductor film and on the part of the monocrystalline semiconductor layer respectively until monocrystalline semiconductor film is in contact with the second polycrystalline semiconductor film, with a second insulating film selectively formed on the monocrystalline semiconductor film with leaving a part thereof to be exposed.

Method of manufacturing a bipolar transistor having thin base region

A fundamental limit to the scaling of CMOS supply voltages (Vcc) exists due to the statistical variation of MOSFET threshold voltage (VT ). At the microscopic (device-to-device) level, an inherent variability in T exists due tothe randomness of the number of dopants in the depletion region of the MOSFET. As the number of dopants in the depletion region decreases with scaling, the VT variations will increase and become more significant. In addition to thisfundamental variation in VT systematic T variations exist due to manufacturing fluctuations with thegate length, gateoxide thickness, implant uniformity, and anneal temperatures. For SRAJvI circuits, the T mismatch causedby channeldopant fluctuations degrades the cell stability and limits the minimum operating voltage of the SRAM. For logic circuits,the systematic VT variations across a wafer significantly increase the variation of the measuredpropagation delay on a wafer as is scaled down towards the MOSFET VT . These limitations on scaling pose additional challenges in thedesign and manufacturing of devices and circuits for low-power systems.Keywords: sub-tm CMOS scaling, threshold-voltage fluctuations, supply-voltage scaling, dopant density fluctuations

Statistical threshold-voltage variation and its impact on supply-voltage scaling

The invention is a semiconductor memory structure having an electrically conductive substrate interconnect formed to provide electrical continuity between a buried contact region and a source/drain region of a transistor without overlap of the buried contact region with the source/drain region. The electrically conductive substrate interconnect is formed during an ion bombardment of the substrate wherein the ions enter the substrate at an oblique angle and underlie at least a portion of a region utilized to control the amount of ions entering the substrate.

Electrically conductive substrate interconnect continuity region and method of forming same with an angled implant

A loss of silicon in active source/drain regions of CMOS transistors can be observed during nitride spacer etch processes, employing CH3F/O2/He based chemistries in high density plasmas. This phenomenon, the so-called “silicon recess”, is a key criterion for the subsequent steps involved in the transistor fabrication process. In this work, the authors compare two CH3F/O2/He spacer etch processes typically used in industry. The mechanism for high Si3N4/Si selectivity is identified as the creation of a SiOxFy passivation layer, generated at the silicon surface. Using in situ ellipsometry and angle resolved x-ray photoelectron spectroscopy, the authors demonstrate that the oxidized layer which leads to silicon recess is driven by the ion energy. Moreover, in the case of high ion energy processes, implanted carbon has been identified under the SiOxFy passivation layer.

Patterning of silicon nitride for CMOS gate spacer technology. I. Mechanisms involved in the silicon consumption in CH3F/O2/He high density plasmas

A buried contact in a semiconductor device is formed by forming an oxide layer on a surface of a semiconductor substrate. A heavily-doped polysilicon layer is formed over the oxide layer and selectively etched to leave a first portion of the polysilicon layer over the surface and remove a second portion of the polysilicon layer from over the surface. The remaining first portion of polysilicon has a vertical surface which is over the surface of the substrate. After this step there is oxide between the first portion of the polysilicon layer and the substrate. An isotropic etch is performed which removes a portion of the oxide between the first portion of the polysilicon layer and the substrate to leave a void between the first portion of the polysilicon layer and the surface of the substrate from the vertical surface of the first portion of the polysilicon to a predetermined distance from the vertical surface of the first portion of the polysilicon layer. A polysilicon layer is then deposited which fills the void with polysilicon. The polysilicon which is not filling the void is removed. An implant is then performed using the first portion of the polysilicon layer as a mask to form a first doped region in the substrate adjacent to the vertical surface of the first portion of the polysilicon layer. Because the polysilicon layer was doped, dopant from the first portion of the polysilicon layer migrates down through the polysilicon filling the void to form a second doped region in the substrate under the first portion of the polysilicon layer which merges with the first doped region in the substrate. This has the effect making electrical contact between the first portion of the polysilicon layer and the first doped region in the substrate and thus achieving a desired buried contact.

Method for forming a buried contact

A new leakage mechanism that is a strong function of substrate bias has been observed on lightly doped drain (LDD) MOSFETs. The substrate bias dependence on this drain-to-substrate leakage current is shown to be related to the formation of sidewall spacers. Devices with a conventional oxide spacer exhibit substrate-bias-dependent leakage with a wide variation in leakage characteristics. Devices with a disposable spacer, however, do not exhibit such leakage and have a small variation in leakage characteristics. The deleterious leakage characteristics observed with conventional oxide spacers are caused by defects produced in the silicon along the spacer edge during spacer formation. These defects can be avoided with a spacer formation process that does not etch into silicon in the source/drain regions. >

Substrate bias dependent leakage in LDD MOSFETs

In order to lower manufacturing costs and increase performance, static random access memory (SRAM) bit cells are scaled progressively toward submicron geometries. The reliability of an SRAM is highly dependent on the bit cell stability. Smaller memory cells with less capacitance and restoring current make the array more susceptible to failures from defectivity, alpha hits, and other instabilities and leakage mechanisms. Improving long term reliability while migrating to higher density devices makes the task of building in and improving reliability increasingly difficult. Reliability requirements for high density SRAMs are very demanding with failure rates of less than 100 failures per billion device hours (100 FITs) being a common criteria. Design techniques for increasing bit cell stability and manufacturability must be implemented in order to build in this level of reliability. Several types of analyses are performed to benchmark the performance of the SRAM device. Examples of these analysis techniques which are presented here include DC parametric measurements of test structures, functional bit mapping of the circuit used to characterize the entire distribution of bits, electrical microprobing of weak and/or failing bits, and system and accelerated soft error rate measurements. These tests allow process and design improvements to be evaluated prior to implementation on the final product. These results are used to provide comprehensive bit cell characterization which can then be compared to device models and adjusted accordingly to provide optimized cell stability versus cell size for a particular technology. The result is designed in reliability which can be accomplished during the early stages of product development.

Implications of scaling on static RAM bit cell stability and reliability

A new multilevel metal failure mechanism is presented in the context of improved manufacturing and reliability. Device failures, with electrical overstress (EOS) characteristics, are shown to be caused by metal-to-metal shorts. These shorts occur when lower metal extrudes through vias and creates upper layer metal protrusions. The metal protrusions can produce immediate or time dependent shorts to closely spaced adjacent metal lines. The metal migration that forms the protrusion failures is unrelated to classical electromigration. This mechanism is unique in that the physical stresses associated with the fabrication process/materials dominates the creation of these protrusions and failures happen without any significant component of electromigration. Effects of stresses from fabrication will be discussed including: sintering conditions, interlevel dielectric properties, and metal system composition. Reliability studies are shown to support the theory that the accelerated lifetest failures from this mechanism occur when a thin oxide breaks down between the protrusion and its adjacent metal line.© (1993) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Lifetest IC failures due to metal extrusion and migration resulting from process-induced stress relief

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Papers

Method for forming a buried contact

Substrate bias dependent leakage in LDD MOSFETs

Implications of scaling on static RAM bit cell stability and reliability

Lifetest IC failures due to metal extrusion and migration resulting from process-induced stress relief