Many modern computer systems and most multicore chips (chip multiprocessors) support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both highlevel concepts as well as specific, concrete examples from real-world systems. Table of Contents: Preface / Introduction to Consistency and Coherence / Coherence Basics / Memory Consistency Motivation and Sequential Consistency / Total Store Order and the x86 Memory Model / Relaxed Memory Consistency / Coherence Protocols / Snooping Coherence Protocols / Directory Coherence Protocols / Advanced Topics in Coherence / Author Biographies

/pdf/a-primer-on-memory-consistency-and-cache-coherence-4cn8rqoyia.pdf

A Primer on Memory Consistency and Cache Coherence

Data management in wireless sensor networks has been an area of significant research in recent years. Many existing sensor data management systems view sensor data as a continuous stream that is sensed, filtered, processed, and aggregated as it “flows” from sensors to users. We argue that technology trends in flash memories and embedded platforms call for re-thinking this architecture. We articulate a vision of a storage-centric sensor network where sensor nodes will be equipped with high-capacity and energy-efficient local flash storage. We argue that the data management infrastructure will need substantial redesign to fully exploit the presence of local storage and processing capability in order to reduce expensive communication. We then describe how StonesDB enables this vision through a number of innovative features including energyefficient use of flash memory, multi-resolution storage and aging, query processing, and intelligent caching.

/pdf/rethinking-data-management-for-storage-centric-sensor-4zs7fnbu3c.pdf

Rethinking Data Management for Storage-centric Sensor Networks.

Verifying Properties of Parallel Programs : An Axiomatic Approach

Objective. Myoelectric activity volitionally generated by the user is often used for controlling hand prostheses in order to replicate the synergistic actions of muscles in healthy humans during grasping. Muscle synergies in healthy humans are based on the integration of visual perception, heuristics and proprioception. Here, we demonstrate how sensor fusion that combines artificial vision and proprioceptive information with the high-level processing characteristics of biological systems can be effectively used in transradial prosthesis control. Approach. We developed a novel context- and user-aware prosthesis (CASP) controller integrating computer vision and inertial sensing with myoelectric activity in order to achieve semi-autonomous and reactive control of a prosthetic hand. The presented method semi-automatically provides simultaneous and proportional control of multiple degrees-of-freedom (DOFs), thus decreasing overall physical effort while retaining full user control. The system was compared against the major commercial state-of-the art myoelectric control system in ten able-bodied and one amputee subject. All subjects used transradial prosthesis with an active wrist to grasp objects typically associated with activities of daily living. Main results. The CASP significantly outperformed the myoelectric interface when controlling all of the prosthesis DOF. However, when tested with less complex prosthetic system (smaller number of DOF), the CASP was slower but resulted with reaching motions that contained less compensatory movements. Another important finding is that the CASP system required minimal user adaptation and training. Significance. The CASP constitutes a substantial improvement for the control of multi-DOF prostheses. The application of the CASP will have a significant impact when translated to real-life scenarious, particularly with respect to improving the usability and acceptance of highly complex systems (e.g., full prosthetic arms) by amputees.

https://iopscience.iop.org/article/10.1088/1741-2560/12/6/066022/pdf

Sensor fusion and computer vision for context-aware control of a multi degree-of-freedom prosthesis.

It has become fairly standard in the programming-languages research world to verify functional programs in proof assistants using induction, algebraic simplification, and rewriting. In this paper, we introduce Kami, a Coq library that enables similar expressive and modular reasoning for hardware designs expressed in the style of the Bluespec language. We can specify, implement, and verify realistic designs entirely within Coq, ending with automatic extraction into a pipeline that bottoms out in FPGAs. Our methodology, using labeled transition systems, has been evaluated in a case study verifying an infinite family of multicore systems, with cache-coherent shared memory and pipelined cores implementing (the base integer subset of) the RISC-V instruction set.

https://dl.acm.org/doi/pdf/10.1145/3110268

Kami: a platform for high-level parametric hardware specification and its modular verification

The goal of this work is to design cache coherence protocols with many cores that can be verified with state-of-the-art automated verification methodologies. In particular, we focus on flat (non-hierarchical) coherence protocols, and we use a mostly-automated methodology based on parametric verification (PV). We propose several design guidelines that architects should follow if they want to design protocols that can be parametrically verified. We experimentally evaluate performance, storage overhead, and scalability of a protocol verified with PV compared to a highly optimized protocol that cannot be verified with PV.

/pdf/pvcoherence-designing-flat-coherence-protocols-for-scalable-2xainsf044.pdf

PVCoherence: Designing flat coherence protocols for scalable verification

The goal of this work is to design cache coherence protocols with many cores such that they can be verified with existing verification methodologies. In particular, the authors focus on flat (nonhierarchical) coherence protocols using a mostly automated methodology based on parametric verification. They present design guidelines that, if followed by architects, enable parametric verification of protocols with arbitrary numbers of cores.

PVCoherence: Designing Flat Coherence Protocols for Scalable Verification

The lack of appropriate models is often the biggest hurdle in applying formal methods in the industry Creating executable models of industrial designs is a challenging task, one that we believe has not been sufficiently addressed by existing research We address this problem for distributed message passing protocols by showing how to synthesize executable models of such protocols from transaction message flows, which are readily available in architecture descriptions We present industrial case studies showing that this approach to creating formal models is effective in practice We also show that going the other way, ie, extracting flows from executable models, is at least as hard as the model-checking problem These results indicate that transaction flows may provide a superior approach to capture design intent than executable models

/pdf/transaction-flows-and-executable-models-formalization-and-2szyeg1jb6.pdf

Transaction flows and executable models: formalization and analysis of message-passing protocols

This paper presents a practical method and associated tool for verifying deadlock freedom properties in guarded command systems. Such properties are expressed in CTL as AGEFi¾? q where q is a set of quiescent states. We require the user to provide transitions of the system that are "helpful" in reaching quiescent states. The distributed search constructs a path consisting of helpful transitions from each reachable state to a state that is either quiescent or is known to have a path to a quiescent state. We extended the PReach model-checker with these algorithms. Performance measurements on both academic and industrial large-scale models shows that the overhead of checking deadlock-freedom compared with state-space enumeration alone is small.

/pdf/distributed-explicit-state-model-checking-of-deadlock-4am1stu2as.pdf

Distributed Explicit State Model Checking of Deadlock Freedom

We present Preach, an industrial strength distributed explicit state model checker based on Murphi. The goal of this project was to develop a reliable, easy to maintain, scalable model checker that was compatible with the Murphi specification language. Preach is implemented in the concurrent functional language Erlang, chosen for its parallel programming elegance. We use the original Murphifront-end to parse the model description, a layer written in Erlang to handle the communication aspects of the algorithm, and also use Murphias a back-end for state expansion and to store the hash table. This allowed a clean and simple implementation, with the core parallel algorithms written in under 1000 lines of code. This paper describes the Preach implementation including the various features that are necessary for the large models we target. We have used Preach to model check an industrial cache coherence protocol with approximately 30 billion states. To our knowledge, this is the largest number published for a distributed explicit state model checker. Preach has been released to the public under an open source BSD license.

Industrial Strength Distributed Explicit State Model Checking

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