Assertion-based verification (ABV) is a critical method for ensuring design circuits comply with their architectural specifications, which are typically described in natural language. This process often requires significant interpretation by engineers to convert these specifications into functional verification assertions. Existing methods for generating assertions from natural language specifications are limited to sentences extracted by engineers, discouraging the practical application. In this work, we present AssertLLM, an automatic assertion generation framework for complete specification files. AssertLLM breaks down the complex task into three phases, incorporating three customized Large Language Models (LLMs) for extracting structural specifications, mapping signal definitions, and generating assertions. Additionally, we provide an open-source benchmark for assessing assertion generation capabilities. Our evaluation of AssertLLM on a full design, encompassing 23 signals, demonstrates that 89% of the generated assertions are both syntactically and functionally accurate.

pdf/assertllm-generating-and-evaluating-hardware-verification-1s5kua3qqm.pdf

AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs

The globalization of the System-on-Chip (SoC) design process has made hardware designs prone to many security vulnerabilities. One of the most critical security vulnerabilities is information leakage (IL), which allows an attacker to gain access to a design’s secret information. IL vulnerabilities can result from unintended design flaws or the intentional insertion of malicious functionality into the design. Such vulnerabilities should be identified at the early design stages to secure a hardware design. Property-driven security verification has emerged as a promising method of verifying that such security vulnerabilities do not exist. This verification technique requires developing an appropriate set of assertions to formally represent the properties. However, forming a comprehensive set of assertions that can cover all potential vulnerabilities in design is challenging. Assertion generation cannot be done manually due to the large complexity of designs, lack of security experts as well as the existence of untrusted observable points in the design. In this work, we propose AGILE, a framework to automatically generate security assertions for property-driven verification to identify IL-based vulnerabilities. The experimental results show that the assertions provided by AGILE can detect both intentional and unintentional IL paths in the input design. We demonstrate the effectiveness of AGILE on the NIST standard, Trust-Hub, and OpenCores benchmarks. Moreover, we use code coverage analysis to evaluate the accessibility of the generated assertions to the source code. The analytical result indicates that by utilizing the assertions generated by AGILE, security coverage of the design under verification (DUV) can be improved significantly.

AGILE: Automated Assertion Generation to Detect Information Leakage Vulnerabilities

—Even if model-driven techniques have been enabled the centrality of the models in automated development processes, the majority of the industrial settings does not embrace such a paradigm due to the procedural complexity of managing model life cycle. This paper proposes a semi-automatic approach for the completion of high-level models of critical systems. The proposal suggests a speciﬁcation guidelines that starts from a partial SysML (Systems Modeling Language) model of a system and on a set of requirements, expressed in the well-known Behaviour- Driven Design paradigm. On the base of such requirements, the approach enables the automatic generation of SysML state machines fragments. Once completed, the approach also enables the modeller to check the results improving the quality of the model and avoiding errors both coming from the mis-interpretation of the tool and from the modeller himself/herself. An example taken from the railway domain shows the approach.

Towards Automatic Model Completion: from Requirements to SysML State Machines

Due to the effectiveness of assertion based verification (ABV) in programmable logic verification, and the error-proneness and time-consuming of the manual writing of assertions, the research on automatic generation of System Verilog Assertion (SVA) from English has developed rapidly in the past decade. The demand for high reliability verification in the aerospace industry urges us to explore the role of automatic assertion generation in Chinese. In this work, we proposed a controlled Chinese natural language (CCNL) framework to translate natural language assertions (NLA) into SVA. The step of capturing controlled Chinese NLAs from specification documents remains manually, which is the reason for so-called semi-automatic generation. CCNL framework consists of Chinese controlled word list, regular expression based semantic parser and assertion translator. We used this framework to extract assertions from requirements documents in Chinese, evaluated the framework, and proved its effectiveness.

(Semi) Automatic Assertion Generation from Controlled Chinese Natural Language: A Practice in Aerospace Industry

We explore contemporary natural language processing (NLP) techniques for converting NL specifications found in design documents directly to an temporal logic-like intermediate representation (IR). Generally, attempts to use NLP for assertion generation have relied on restrictive sentence formats and grammars as well as being difficult to handle new sentence formats. We tackle these issues by first implementing a system that uses commonsense mappings to process input sentences into a normalized form. Then we use frame semantics to convert the normalized sentences into an IR based on the information and context contained in the Frames. Through this we are able to handle a large number of sentences from real datasheets allowing for complex formats using temporal conditions, property statements, and compound statements; all order agnostic. Our system can also be easy extended by modifying an external, rather than internal, commonsense knowledge-base to handle new sentence formats without requiring code changes or intimate knowledge of the algorithms used.

Automated Assertion Generation from Natural Language Specifications

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Automated Assertion Generation from Natural Language Specifications